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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020utm-pc.dtsi45 /* 256KB for DTB Image */
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
H A Dp1025twr.dtsi53 /* 256KB for Vitesse 7385 Switch firmware */
60 /* 256KB for DTB Image */
79 /* 256KB for QE ucode firmware*/
87 /* 512KB for u-boot Bootloader Image */
88 /* 512KB for u-boot Environment Variables */
H A Dp1020mbg-pc.dtsi45 /* 128KB for DTB Image */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
/openbmc/linux/Documentation/mm/
H A Dvmemmap_dedup.rst20 currently supported. Since the base page size on x86 is 4KB, a 2MB HugeTLB page
41 | x86-64 | 4KB | 2MB | 1GB | | |
43 | | 4KB | 64KB | 2MB | 32MB | 1GB |
45 | arm64 | 16KB | 2MB | 32MB | 1GB | |
47 | | 64KB | 2MB | 512MB | 16GB | |
/openbmc/u-boot/board/freescale/t1040qds/
H A Dt1040_pbi.cfg6 #Configure CPC1 as 256KB SRAM
/openbmc/u-boot/doc/
H A DREADME.mpc85xx-spin-table5 accessible for core 0. It is part of release.S, within 4KB range after
12 page translation for secondary cores to use this page of memory. Then 4KB
/openbmc/u-boot/board/freescale/t4rdb/
H A Dt4_pbi.cfg12 #512KB SRAM
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dt1024_pbi.cfg6 #Configure CPC1 as 256KB SRAM
/openbmc/u-boot/board/freescale/t102xqds/
H A Dt1024_pbi.cfg6 #Configure CPC1 as 256KB SRAM
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/zram/zram/
H A Dzram-swap-init25 zramctl -a ${ZRAM_ALGORITHM} -s ${memzram}KB $device
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor-lazor-r1-kb.dts11 model = "Google Lazor (rev1 - 2) with KB Backlight";
H A Dsc7180-trogdor-lazor-r9-kb.dts16 model = "Google Lazor (rev9+) with KB Backlight";
/openbmc/linux/Documentation/devicetree/bindings/pmem/
H A Dpmem-region.txt47 * This node specifies one 4KB region spanning from
56 * This node specifies two 4KB regions that are backed by
/openbmc/linux/lib/zstd/compress/
H A Dzstd_compress_literals.c80 size_t const lhSize = 3 + (srcSize >= 1 KB) + (srcSize >= 16 KB); in ZSTD_compressLiterals()
/openbmc/u-boot/arch/x86/
H A DKconfig255 bool "512 KB"
257 Choose this option if you have a 512 KB ROM chip.
260 bool "1024 KB (1 MB)"
262 Choose this option if you have a 1024 KB (1 MB) ROM chip.
265 bool "2048 KB (2 MB)"
267 Choose this option if you have a 2048 KB (2 MB) ROM chip.
270 bool "4096 KB (4 MB)"
272 Choose this option if you have a 4096 KB (4 MB) ROM chip.
275 bool "8192 KB (8 MB)"
280 bool "16384 KB (16 MB)"
[all …]
/openbmc/u-boot/board/freescale/b4860qds/
H A Db4_pbi.cfg6 #Configure CPC1 as 512KB SRAM
/openbmc/qemu/docs/system/arm/
H A Dmusicpal.rst9 - 32 MB RAM, 256 KB SRAM, 8 MB flash.
/openbmc/linux/Documentation/arch/xtensa/
H A Dmmu.rst83 | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
126 | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
170 | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
/openbmc/linux/arch/alpha/kernel/
H A Dpci.c122 #define KB 1024 macro
123 #define MB (1024*KB)
186 #undef KB
H A Dsmc37c93x.c23 #define KB 1024 macro
24 #define MB (1024*KB)
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
109 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
215 the RK3188, the first 1KB of the first stage are loaded
229 the RK3188, the first 1KB of the first stage are loaded
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_cyclone5.dtsi7 /* First 4KB has trampoline code for secondary cores. */
H A Dsocfpga_arria5.dtsi7 /* First 4KB has trampoline code for secondary cores. */
/openbmc/linux/tools/bootconfig/scripts/
H A Dbconf2ftrace.sh235 *KB)
236 echo ${1%KB};;
/openbmc/u-boot/board/freescale/t104xrdb/
H A Dt104x_pbi.cfg16 #Configure CPC1 as 256KB SRAM

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