1ffd06e02SYork SunSpin table in cache 2ffd06e02SYork Sun===================================== 3ffd06e02SYork SunAs specified by ePAPR v1.1, the spin table needs to be in cached memory. After 4*a187559eSBin MengDDR is initialized and U-Boot relocates itself into DDR, the spin table is 5ffd06e02SYork Sunaccessible for core 0. It is part of release.S, within 4KB range after 6ffd06e02SYork Sun__secondary_start_page. For other cores to use the spin table, the booting 7ffd06e02SYork Sunprocess is described below: 8ffd06e02SYork Sun 9ffd06e02SYork SunCore 0 sets up the reset page on the top 4K of memory (or 4GB if total memory 10ffd06e02SYork Sunis more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of 11ffd06e02SYork Sunthe physical address of this page, with WIMGE=0b01010. Core 0 also enables boot 12ffd06e02SYork Sunpage translation for secondary cores to use this page of memory. Then 4KB 13ffd06e02SYork Sunmemory is copied from __secondary_start_page to the boot page, after flusing 14ffd06e02SYork Suncache because this page is mapped as normal DDR. Before copying the reset page, 15ffd06e02SYork Suncore 0 puts the physical address of the spin table (which is in release.S and 16ffd06e02SYork Sunrelocated to the top of mapped memory) into a variable __spin_table_addr so 17ffd06e02SYork Sunthat secondary cores can see it. 18ffd06e02SYork Sun 19ffd06e02SYork SunWhen secondary cores boot up from 0xffff_f000 page, they only have one default 20ffd06e02SYork SunTLB. While booting, they set up another TLB in AS=1 space and jump into 21ffd06e02SYork Sunthe new space. The new TLB covers the physical address of the spin table page, 22ffd06e02SYork Sunwith WIMGE =0b00100. Now secondary cores can keep polling the spin table 23ffd06e02SYork Sunwithout stress DDR bus because both the code and the spin table is in cache. 24ffd06e02SYork Sun 25ffd06e02SYork SunFor the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep 26ffd06e02SYork Suncache coherence. 27