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/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dxlnx,zynqmp-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq MPSoC Power Management
10 - Michal Simek <michal.simek@amd.com>
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
28 that will be the phandle to the intended sub-mailbox
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
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H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
14 #include "zynqmp.dtsi"
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
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H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU111
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU106
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/openbmc/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
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/openbmc/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
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H A Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
20 - $ref: ../dma-controller.yaml#
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
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/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,zynqmp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 ZynqMP's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
31 const: xlnx,zynqmp-pinctrl
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-zynqmp-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,versal-qspi-1.0
19 - xlnx,zynqmp-qspi-1.0
27 clock-names:
29 - const: ref_clk
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/openbmc/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2018, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/phy/phy.h>
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/openbmc/qemu/hw/microblaze/
H A Dxlnx-zynqmp-pmu.c2 * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
20 #include "exec/address-spaces.h"
25 #include "hw/intc/xlnx-zynqmp-ipi.h"
26 #include "hw/intc/xlnx-pmu-iomod-intc.h"
31 #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx-zynqmp-pmu-soc"
64 object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU); in xlnx_zynqmp_pmu_soc_init()
66 object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC); in xlnx_zynqmp_pmu_soc_init()
71 object_initialize_child(obj, name, &s->ipi[i], TYPE_XLNX_ZYNQMP_IPI); in xlnx_zynqmp_pmu_soc_init()
80 object_property_set_uint(OBJECT(&s->cpu), "base-vectors", in xlnx_zynqmp_pmu_soc_realize()
82 object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true, in xlnx_zynqmp_pmu_soc_realize()
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/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
14 special extensions to add functionality, is a high-performance dual-port
21 const: ceva,ahci-1v84
29 dma-coherent: true
37 power-domains:
40 ceva,p0-cominit-params:
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/openbmc/linux/Documentation/driver-api/xilinx/
H A Deemi.rst6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
13 ----------------------------------------------
16 device to communicate with a power management controller (PMC) on a
17 device to issue or respond to power management requests.
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
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