|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33 |
|
| #
ee6c637f |
| 08-Jun-2023 |
Manikanta Guntupalli <manikanta.guntupalli@amd.com> |
arm64: zynqmp: Fix open drain warning on ZynqMP
Mark both GPIO lines as GPIO_OPEN_DRAIN which is required by i2c-gpio DT
binding. Similar change was done by commit 8df80c1801c9 ("ARM: dts: exynos:
C
arm64: zynqmp: Fix open drain warning on ZynqMP
Mark both GPIO lines as GPIO_OPEN_DRAIN which is required by i2c-gpio DT
binding. Similar change was done by commit 8df80c1801c9 ("ARM: dts: exynos:
Convert to new i2c-gpio bindings").
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a0faf488dde310e1c1c1a676c371e223db6bdca6.1686227712.git.michal.simek@amd.com
show more ...
|
|
Revision tags: v6.1.32, v6.1.31, v6.1.30 |
|
| #
1d831cad |
| 22-May-2023 |
Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> |
arm64: zynqmp: Set qspi tx-buswidth to 4
All ZynqMP boards are setting up tx-buswidth to 1. Due to this the
framework only issues 1-1-1 write commands to the GQSPI driver. But the
GQSPI controller i
arm64: zynqmp: Set qspi tx-buswidth to 4
All ZynqMP boards are setting up tx-buswidth to 1. Due to this the
framework only issues 1-1-1 write commands to the GQSPI driver. But the
GQSPI controller is capable of handling 1-4-4 write commands, so updated
the tx-buswidth to 4.
Using all 4 lines will increase the tx data transfer rate, as now the
tx data will be transferred on four lines instead on single line.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
show more ...
|
| #
f8673fd5 |
| 22-May-2023 |
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> |
arm64: zynqmp: Fix usb node drive strength and slew rate
As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
str
arm64: zynqmp: Fix usb node drive strength and slew rate
As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb group pins.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/379071f44ceb27a0e32d74e13221640922d989d1.1684767562.git.michal.simek@amd.com
show more ...
|
| #
c720a1f5 |
| 22-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Describe TI phy as ethernet-phy-id
TI DP83867 is using strapping based on MIO pins. Tristate setup can
influence PHY address. That's why switch description with ethernet-phy-id
compat
arm64: zynqmp: Describe TI phy as ethernet-phy-id
TI DP83867 is using strapping based on MIO pins. Tristate setup can
influence PHY address. That's why switch description with ethernet-phy-id
compatible string which enable calling reset. PHY itself setups phy address
after power up or reset. Phy reset is done via gpio.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b49904649a363f40dc9c4d3fa275e42129562082.1684767562.git.michal.simek@amd.com
show more ...
|
| #
4e4ddd3d |
| 30-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Krzysztof Kozlowski <krzy
arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
show more ...
|
|
Revision tags: v6.1.29, v6.1.28 |
|
| #
255118de |
| 02-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Enable AMS on SOM and other zcu10x boards
AMS is used for monitoring system. Used for measuring voltages and
especially temperatures. Origin interface is IIO but via iio-hwmon it can
arm64: zynqmp: Enable AMS on SOM and other zcu10x boards
AMS is used for monitoring system. Used for measuring voltages and
especially temperatures. Origin interface is IIO but via iio-hwmon it can
be moved to hwmon framework too (done for SOM and zcu100).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e1e1621ac1cee7f36ef20606bb3795e130de9609.1683034376.git.michal.simek@amd.com
show more ...
|
|
Revision tags: v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21 |
|
| #
37e78949 |
| 21-Mar-2023 |
Parth Gajjar <parth.gajjar@amd.com> |
arm64: zynqmp: Add mali-400 gpu node for zynqmp
Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.
Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar
arm64: zynqmp: Add mali-400 gpu node for zynqmp
Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.
Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
|
|
Revision tags: v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48 |
|
| #
228e8a88 |
| 15-Jun-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: xilinx: align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).
Signed-off-by: Krzysztof Kozlowski
arm64: dts: xilinx: align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220616005333.18491-30-krzysztof.kozlowski@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
|
|
Revision tags: v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60 |
|
| #
b61c4ff9 |
| 06-Aug-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards
The commit 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms")
finally add proper support for Xilinx dwc3 driver. This patch i
arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards
The commit 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms")
finally add proper support for Xilinx dwc3 driver. This patch is adding DT
description for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michael Tretter <m.tretter@pengutronix.de>
Link: https://lore.kernel.org/r/640a3bc0dc3e32560d3e84c2f78b5ae561396eb0.1628244703.git.michal.simek@xilinx.com
show more ...
|
| #
adc40ff8 |
| 06-Aug-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Remove not documented is-dual property
Remove is-dual not documented property and also update comment about QSPI
sizes to reflect dual configuration as 16MB + 16MB.
Only single config
arm64: zynqmp: Remove not documented is-dual property
Remove is-dual not documented property and also update comment about QSPI
sizes to reflect dual configuration as 16MB + 16MB.
Only single configuration is supported now.
Reported-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/876c53b92f99623bae45d5c0c5ae79ee3e24f745.1628239345.git.michal.simek@xilinx.com
show more ...
|
|
Revision tags: v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46 |
|
| #
56e54601 |
| 14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Wire qspi on multiple boards
Couple of boards have qspi on the board that's why enable controller and
describe them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https
arm64: zynqmp: Wire qspi on multiple boards
Couple of boards have qspi on the board that's why enable controller and
describe them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com
show more ...
|
| #
1d4bd118 |
| 14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add note about UHS mode on some boards
Add note about UHS mode and add no-1-8-v property to zc1751-dc1 board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore
arm64: zynqmp: Add note about UHS mode on some boards
Add note about UHS mode and add no-1-8-v property to zc1751-dc1 board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/462b95844e7aedb00768035913265d7af90c3b2f.1623684253.git.michal.simek@xilinx.com
show more ...
|
| #
58ccd7e8 |
| 14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: List reset property for ethernet phy
Add information about reset gpio for ethernet phy in case someone wants to
use it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: ht
arm64: zynqmp: List reset property for ethernet phy
Add information about reset gpio for ethernet phy in case someone wants to
use it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/e153f0cda37a2a6ea1c6e11fb0a4af1d400f29e2.1623684253.git.michal.simek@xilinx.com
show more ...
|
| #
d65ec93f |
| 14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add nvmem alises for eeproms
Use nvmem alias to point to eeprom memory which contains information about
board. The change is done based on discussion in the link below.
Link: https:/
arm64: zynqmp: Add nvmem alises for eeproms
Use nvmem alias to point to eeprom memory which contains information about
board. The change is done based on discussion in the link below.
Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/9b860b47ec3ca64340b4d29317e92b667236d7d1.1623684253.git.michal.simek@xilinx.com
show more ...
|
| #
bef1e3f5 |
| 14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Remove additional newline
This is sync between Linux and U-Boot. Trivial change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/16f6f41c8d748d3
arm64: zynqmp: Remove additional newline
This is sync between Linux and U-Boot. Trivial change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/16f6f41c8d748d3c7cd4f49b2839e63a5b41c944.1623684253.git.michal.simek@xilinx.com
show more ...
|
| #
8b698f1b |
| 14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add phy description for usb3.0
usb3.0 requires serdes setting that's why also wire it up.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/cd856e
arm64: zynqmp: Add phy description for usb3.0
usb3.0 requires serdes setting that's why also wire it up.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/cd856e5f87bc967373691d04e79de3d0022ef424.1623684253.git.michal.simek@xilinx.com
show more ...
|
| #
c821045f |
| 14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add pinctrl description for all boards
The commit 1dccb5ec0123 ("dt-bindings: pinctrl: Add binding for ZynqMP
pinctrl driver") and commit 8b242ca700f8 ("pinctrl: Add Xilinx ZynqMP
pin
arm64: zynqmp: Add pinctrl description for all boards
The commit 1dccb5ec0123 ("dt-bindings: pinctrl: Add binding for ZynqMP
pinctrl driver") and commit 8b242ca700f8 ("pinctrl: Add Xilinx ZynqMP
pinctrl driver support") add support for Xilinx ZynqMP pinctrl driver
that's why describe pins configuration for current boards.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d8bc42600da85f5a23d977d4b61e6528720573e5.1623684253.git.michal.simek@xilinx.com
show more ...
|
|
Revision tags: v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22 |
|
| #
73d677e9 |
| 08-Mar-2021 |
Quanyang Wang <quanyang.wang@windriver.com> |
arm64: dts: zynqmp: Remove si5328 device nodes
The function of_i2c_get_board_info will call of_modalias_node to check
if a device_node contains "compatible" string. But for the device si5328
at zcu1
arm64: dts: zynqmp: Remove si5328 device nodes
The function of_i2c_get_board_info will call of_modalias_node to check
if a device_node contains "compatible" string. But for the device si5328
at zcu102/zcu106 boards, there is no proper DT bindings for them. So remove
si5328 device nodes from dts files to eliminate the error info in the boot
message:
i2c i2c-10: of_i2c: modalias failure on /axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69
i2c i2c-10: Failed to create I2C device for /axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Link: https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.wang@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
|
Revision tags: v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
|
| #
55563399 |
| 21-Jan-2021 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
arm64: dts: zynqmp: Wire up the DisplayPort subsystem
Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.
Signed-off-by: Laurent Pinchart <laurent.pi
arm64: dts: zynqmp: Wire up the DisplayPort subsystem
Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/9769d4d103b6eb75e3324825117f6832a746004e.1611232558.git.michal.simek@xilinx.com
show more ...
|
| #
63481699 |
| 21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis
Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with
0 value to have it listed in case that files are copied to d
arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis
Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/dbdfcc1b25af8b28fc658a37ce18902978cb410d.1611224800.git.michal.simek@xilinx.com
show more ...
|
| #
51733f16 |
| 21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
Enable psgtr driver and write clocks property to get sata to work.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link:
arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
Enable psgtr driver and write clocks property to get sata to work.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/80b52ef97501968ee97fc152363bc4b9b7bb2cff.1611224800.git.michal.simek@xilinx.com
show more ...
|
| #
928a5747 |
| 21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
Enable si5341 driver is the main chip for providing preprogrammed clocks
for the whole platform.
# cat /sys/kernel/debug/clk/clk_summary
arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
Enable si5341 driver is the main chip for providing preprogrammed clocks
for the whole platform.
# cat /sys/kernel/debug/clk/clk_summary
...
refhdmi 1 1 0 114285000 0 0 50000
xtal_0 0 0 0 114285000 0 0 50000
pll_0 0 0 0 40731174000000 0 0 50000
clk1_0 0 0 0 27000000 0 0 50000
clk0_0 0 0 0 27000000 0 0 50000
ref48M 1 2 0 48000000 0 0 50000
si5341 0 4 0 14000000 0 0 50000
clock-generator.N4 0 0 0 0 0 0 50000
clock-generator.N3 0 1 0 733260000 0 0 50000
clock-generator.9 0 1 0 33330000 0 0 50000
clock-generator.N2 0 1 0 104000000 0 0 50000
clock-generator.2 0 1 0 26000000 0 0 50000
clock-generator.N1 0 2 0 594000000 0 0 50000
clock-generator.7 0 1 0 74250000 0 0 50000
clock-generator.0 0 1 0 27000000 0 0 50000
clock-generator.N0 0 4 0 1000000000 0 0 50000
clock-generator.8 0 0 0 0 0 0 50000
clock-generator.6 0 1 0 125000000 0 0 50000
clock-generator.5 0 1 0 100000000 0 0 50000
clock-generator.4 0 1 0 100000000 0 0 50000
clock-generator.3 0 1 0 125000000 0 0 50000
clock-generator.1 0 0 0 0 0 0 50000
...
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/b93f13297684704a60e8d7274009a20aa98d14f7.1611224800.git.michal.simek@xilinx.com
show more ...
|
| #
82a7ebf0 |
| 21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu10
arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/82b2b13006307f108ace81c50c213c3857078b57.1611224800.git.michal.simek@xilinx.com
show more ...
|
|
Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10 |
|
| #
cbf5a878 |
| 16-Sep-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: xilinx: align GPIO hog names with dtschema
The convention for node names is to use hyphens, not underscores.
dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix.
Signed-off-
arm64: dts: xilinx: align GPIO hog names with dtschema
The convention for node names is to use hyphens, not underscores.
dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916155715.21009-8-krzk@kernel.org
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
|
Revision tags: v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11 |
|
| #
353f5ece |
| 26-Aug-2019 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add label property to all ina226 on zcu102
Label property is adding capability to distiguish chips from each other
when iio framework is used.
Signed-off-by: Michal Simek <michal.sim
arm64: zynqmp: Add label property to all ina226 on zcu102
Label property is adding capability to distiguish chips from each other
when iio framework is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|