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Searched +full:zynqmp +full:- +full:pinctrl (Results 1 – 25 of 29) sorted by relevance

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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
[all …]
H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
[all …]
H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
14 #include "zynqmp.dtsi"
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
[all …]
H A Dzynqmp-sm-k26-revA.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU111
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU106
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
[all …]
H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 si5332_0: si5332-0 { /* u17 */
21 compatible = "fixed-clock";
[all …]
H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,zynqmp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
14 common pinctrl bindings used by client devices, including the meaning of the
17 ZynqMP's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
[all …]
/openbmc/linux/drivers/pinctrl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PINCTRL infrastructure and drivers
6 menuconfig PINCTRL config
9 if PINCTRL
29 bool "Debug PINCTRL calls"
32 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
66 will be called pinctrl-apple-gpio.
69 bool "Axis ARTPEC-6 pin controller driver"
74 This is the driver for the Axis ARTPEC-6 pin controller. This driver
77 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
[all …]
H A Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP pin controller
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
26 #include "pinctrl-utils.h"
47 * struct zynqmp_pmux_function - a pinmux function
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
4 subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
6 obj-y += core.o pinctrl-utils.o
7 obj-$(CONFIG_PINMUX) += pinmux.o
8 obj-$(CONFIG_PINCONF) += pinconf.o
9 obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
10 obj-$(CONFIG_OF) += devicetree.o
12 obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
13 obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o
14 obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o
[all …]
/openbmc/linux/arch/arm64/
H A DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
7 select PINCTRL
12 bool "Allwinner sunxi 64-bit SoC Family"
14 select PINCTRL
33 This enables support for Apple's in-house ARM SoC family, starting
46 select PINCTRL
59 select PINCTRL
67 Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
70 This enables support for Broadcom BCA ARM-based broadband chipsets,
74 bool "Broadcom Set-Top-Box SoCs"
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
16 compatible = "xlnx,zynqmp";
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
[all …]
/openbmc/u-boot/
H A DMAINTAINERS8 W: Web-page with status/info
24 N: [^a-z]tegra all files whose path contains the word tegra
52 -----------------------------------
57 L: uboot-snps-arc@synopsys.com
58 T: git git://git.denx.de/u-boot-arc.git
65 L: uboot-snps-arc@synopsys.com
66 F: drivers/clk/clk-hsdk-cgu.c
67 F: include/dt-bindings/clock/snps,hsdk-cgu.h
68 F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
73 L: uboot-snps-arc@synopsys.com
[all …]
/openbmc/u-boot/arch/arm/
H A DKconfig14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
20 information that is embedded into the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
28 U-Boot typically uses a hard-coded value for the stack pointer
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that can be loaded and executed at arbitrary
41 Place a Linux kernel image header at the start of the U-Boot binary.
45 U-Boot needs to use, but which isn't part of the binary.
74 Do not enable instruction cache in U-Boot
[all …]
/openbmc/linux/drivers/gpio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
47 this symbol, but new drivers should use the generic gpio-regmap
57 non-sleeping contexts. They can make bitbanged serial protocols
118 Enables support for the idio-16 library functions. The idio-16 library
120 ACCES IDIO-16 family such as the 104-IDIO-16 and the PCI-IDIO-16.
122 If built as a module its name will be gpio-idio-16.
128 tristate "GPIO driver for 74xx-ICs with MMIO access"
132 Say yes here to support GPIO functionality for 74xx-compatible ICs
149 If driver is built as a module it will be called gpio-altera.
310 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ----------
[all...]
H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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/openbmc/qemu/pc-bios/
HDu-boot.e500 ... --------------------- ...

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