| /openbmc/linux/Documentation/ABI/stable/ |
| H A D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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| /openbmc/linux/Documentation/devicetree/bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
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| /openbmc/linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | xlnx,zynqmp-power.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
28 that will be the phandle to the intended sub-mailbox
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
37 - description: tx channel
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| /openbmc/linux/Documentation/devicetree/bindings/crypto/ |
| H A D | xlnx,zynqmp-aes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator
10 - Kalyani Akula <kalyani.akula@amd.com>
11 - Michal Simek <michal.simek@amd.com>
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
22 - compatible
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| /openbmc/linux/Documentation/devicetree/bindings/fpga/ |
| H A D | xlnx,zynqmp-pcap-fpga.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
16 firmware interface.
20 const: xlnx,zynqmp-pcap-fpga
23 - compatible
28 - |
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| /openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | xlnx,zynqmp-nvmem.txt | 1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
3 --------------------------------------------------------------------------
5 like soc revision, IDCODE... etc, By using the firmware interface.
8 - compatible: should be "xlnx,zynqmp-nvmem-fw"
14 -------
16 -------
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
23 - items:
24 - enum:
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| /openbmc/linux/drivers/firmware/xilinx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
13 Firmware interface driver is used by different
14 drivers to communicate with the firmware for
16 Say yes to enable ZynqMP firmware interface driver.
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
23 Say yes to enable ZynqMP firmware interface debug APIs.
|
| H A D | zynqmp-debug.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
5 * Copyright (C) 2014-2018 Xilinx, Inc.
19 #include <linux/firmware/xlnx-zynqmp.h>
20 #include "zynqmp-debug.h"
41 * zynqmp_pm_argument_value() - Extract argument value from a PM-API request
42 * @arg: Entered PM-API argument in string format
61 * get_pm_api_id() - Extract API-ID from a PM-API request
62 * @pm_api_req: Entered PM-API argument in string format
63 * @pm_id: API-ID
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | xlnx,zynqmp-gpio-modepin.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ZynqMP Mode Pin GPIO controller
10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
15 - Piyush Mehta <piyush.mehta@amd.com>
19 const: xlnx,zynqmp-gpio-modepin
21 gpio-controller: true
23 "#gpio-cells":
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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| /openbmc/linux/Documentation/driver-api/xilinx/ |
| H A D | eemi.rst | 5 Xilinx Zynq MPSoC Firmware Interface
6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
9 driver provides an interface to firmware APIs. Interface APIs can be
13 ----------------------------------------------
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
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| /openbmc/u-boot/arch/arm/mach-zynqmp/ |
| H A D | Kconfig | 28 default "zynqmp"
35 default "zynqmp"
58 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
61 string "PMU firmware"
65 Include external PMUFW (Platform Management Unit FirmWare) to
69 bool "Configure ZynqMP USB"
90 Include psu_init to full u-boot. SPL include psu_init by default.
|
| /openbmc/linux/drivers/nvmem/ |
| H A D | zynqmp_nvmem.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/nvmem-provider.h>
10 #include <linux/firmware/xlnx-zynqmp.h>
30 dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); in zynqmp_nvmem_read()
37 .name = "zynqmp-nvmem",
45 { .compatible = "xlnx,zynqmp-nvmem-fw", },
52 struct device *dev = &pdev->dev; in zynqmp_nvmem_probe()
57 return -ENOMEM; in zynqmp_nvmem_probe()
59 priv->dev = dev; in zynqmp_nvmem_probe()
65 priv->nvmem = devm_nvmem_register(dev, &econfig); in zynqmp_nvmem_probe()
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| /openbmc/linux/drivers/clk/zynqmp/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
8 Support for the Zynqmp Ultrascale clock controller.
9 It has a dependency on the PMU firmware.
|
| /openbmc/linux/arch/arm64/boot/dts/xilinx/ |
| H A D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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| /openbmc/linux/drivers/fpga/ |
| H A D | zynqmp-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
51 kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); in zynqmp_fpga_ops_write()
53 return -ENOMEM; in zynqmp_fpga_ops_write()
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP pin controller
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
47 * struct zynqmp_pmux_function - a pinmux function
62 * struct zynqmp_pinctrl - driver data
82 * struct zynqmp_pctrl_group - Pin control group info
99 return pctrl->ngroups; in zynqmp_pctrl_get_groups_count()
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| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | xlnx,zynqmp-ipi-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +-------------------------------------+
15 | Xilinx ZynqMP IPI Controller |
16 +-------------------------------------+
17 +--------------------------------------------------+
18 TF-A | |
21 +--------------------------+ |
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| /openbmc/qemu/hw/arm/ |
| H A D | xlnx-zcu102.c | 2 * Xilinx ZynqMP ZCU102 board
20 #include "hw/arm/xlnx-zynqmp.h"
23 #include "qemu/error-report.h"
43 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
51 return s->secure; in OBJECT_DECLARE_SIMPLE_TYPE()
58 s->secure = value; in zcu102_set_secure()
65 return s->virt; in zcu102_get_virt()
72 s->virt = value; in zcu102_set_virt()
84 /* If EL3 is enabled, we keep all firmware nodes active. */ in zcu102_modify_dtb()
85 if (!s->secure) { in zcu102_modify_dtb()
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| /openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/ |
| H A D | trusted-firmware-a_2.11.0.bb | 1 require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc
3 # TF-A v2.11.0
9 # in TF-A src, docs/getting_started/prerequisites.rst lists the expected version mbedtls
10 # mbedtls-3.6.0
18 file://0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch \
19 file://0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch \
|
| H A D | trusted-firmware-a_2.10.4.bb | 1 require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc
3 # TF-A v2.10.4
5 SRCBRANCH = "lts-v2.10"
9 # in TF-A src, docs/getting_started/prerequisites.rst lists the expected version mbedtls
10 # mbedtls-3.4.1
18 file://0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch \
19 file://0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch \
|
| /openbmc/linux/drivers/crypto/xilinx/ |
| H A D | zynqmp-sha.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP SHA Driver.
12 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
55 tfm_ctx->dev = drv_ctx->dev; in zynqmp_sha_init_tfm()
63 tfm_ctx->fbk_tfm = fallback_tfm; in zynqmp_sha_init_tfm()
64 hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm); in zynqmp_sha_init_tfm()
73 if (tfm_ctx->fbk_tfm) { in zynqmp_sha_exit_tfm()
74 crypto_free_shash(tfm_ctx->fbk_tfm); in zynqmp_sha_exit_tfm()
75 tfm_ctx->fbk_tfm = NULL; in zynqmp_sha_exit_tfm()
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | xlnx,zynqmp-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 ZynqMP's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
31 const: xlnx,zynqmp-pinctrl
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| /openbmc/linux/drivers/pmdomain/xilinx/ |
| H A D | zynqmp-pm-domains.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Generic PM domain support
5 * Copyright (C) 2015-2019 Xilinx, Inc.
20 #include <linux/firmware/xlnx-zynqmp.h>
27 * struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
42 * zynqmp_gpd_is_active_wakeup_path() - Check if device is in wakeup source
65 * zynqmp_gpd_power_on() - Power on PM domain
78 ret = zynqmp_pm_set_requirement(pd->node_id, in zynqmp_gpd_power_on()
83 dev_err(&domain->dev, in zynqmp_gpd_power_on()
85 ZYNQMP_PM_CAPABILITY_ACCESS, pd->node_id, ret); in zynqmp_gpd_power_on()
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