1d7f4a65cSPiyush Mehta# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2d7f4a65cSPiyush Mehta%YAML 1.2 3d7f4a65cSPiyush Mehta--- 4*45698208SRob Herring$id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml# 5*45698208SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6d7f4a65cSPiyush Mehta 7d7f4a65cSPiyush Mehtatitle: ZynqMP Mode Pin GPIO controller 8d7f4a65cSPiyush Mehta 9d7f4a65cSPiyush Mehtadescription: 10d7f4a65cSPiyush Mehta PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin 11d7f4a65cSPiyush Mehta GPIO controller with configurable from numbers of pins (from 0 to 3 per 12d7f4a65cSPiyush Mehta PS_MODE). Every pin can be configured as input/output. 13d7f4a65cSPiyush Mehta 14d7f4a65cSPiyush Mehtamaintainers: 15d5c421d2SMichal Simek - Piyush Mehta <piyush.mehta@amd.com> 16d7f4a65cSPiyush Mehta 17d7f4a65cSPiyush Mehtaproperties: 18d7f4a65cSPiyush Mehta compatible: 19d7f4a65cSPiyush Mehta const: xlnx,zynqmp-gpio-modepin 20d7f4a65cSPiyush Mehta 21d7f4a65cSPiyush Mehta gpio-controller: true 22d7f4a65cSPiyush Mehta 23d7f4a65cSPiyush Mehta "#gpio-cells": 24d7f4a65cSPiyush Mehta const: 2 25d7f4a65cSPiyush Mehta 26d7f4a65cSPiyush Mehtarequired: 27d7f4a65cSPiyush Mehta - compatible 28d7f4a65cSPiyush Mehta - gpio-controller 29d7f4a65cSPiyush Mehta - "#gpio-cells" 30d7f4a65cSPiyush Mehta 31d7f4a65cSPiyush MehtaadditionalProperties: false 32d7f4a65cSPiyush Mehta 33d7f4a65cSPiyush Mehtaexamples: 34d7f4a65cSPiyush Mehta - | 35d7f4a65cSPiyush Mehta zynqmp-firmware { 36d7f4a65cSPiyush Mehta gpio { 37d7f4a65cSPiyush Mehta compatible = "xlnx,zynqmp-gpio-modepin"; 38d7f4a65cSPiyush Mehta gpio-controller; 39d7f4a65cSPiyush Mehta #gpio-cells = <2>; 40d7f4a65cSPiyush Mehta }; 41d7f4a65cSPiyush Mehta }; 42d7f4a65cSPiyush Mehta 43d7f4a65cSPiyush Mehta... 44