1d4fd4f01SNobuhiro Iwamatsu# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2d4fd4f01SNobuhiro Iwamatsu%YAML 1.2 3d4fd4f01SNobuhiro Iwamatsu--- 4d4fd4f01SNobuhiro Iwamatsu$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml# 5d4fd4f01SNobuhiro Iwamatsu$schema: http://devicetree.org/meta-schemas/core.yaml# 6d4fd4f01SNobuhiro Iwamatsu 7dd3cb467SAndrew Lunntitle: Xilinx Zynq Ultrascale MPSoC FPGA Manager 8d4fd4f01SNobuhiro Iwamatsu 9d4fd4f01SNobuhiro Iwamatsumaintainers: 10*d5c421d2SMichal Simek - Nava kishore Manne <nava.kishore.manne@amd.com> 11d4fd4f01SNobuhiro Iwamatsu 12d4fd4f01SNobuhiro Iwamatsudescription: | 13d4fd4f01SNobuhiro Iwamatsu Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager. 14d4fd4f01SNobuhiro Iwamatsu The ZynqMP SoC uses the PCAP (Processor Configuration Port) to 15d4fd4f01SNobuhiro Iwamatsu configure the Programmable Logic (PL). The configuration uses the 16d4fd4f01SNobuhiro Iwamatsu firmware interface. 17d4fd4f01SNobuhiro Iwamatsu 18d4fd4f01SNobuhiro Iwamatsuproperties: 19d4fd4f01SNobuhiro Iwamatsu compatible: 20d4fd4f01SNobuhiro Iwamatsu const: xlnx,zynqmp-pcap-fpga 21d4fd4f01SNobuhiro Iwamatsu 22d4fd4f01SNobuhiro Iwamatsurequired: 23d4fd4f01SNobuhiro Iwamatsu - compatible 24d4fd4f01SNobuhiro Iwamatsu 25d4fd4f01SNobuhiro IwamatsuadditionalProperties: false 26d4fd4f01SNobuhiro Iwamatsu 27d4fd4f01SNobuhiro Iwamatsuexamples: 28d4fd4f01SNobuhiro Iwamatsu - | 29d4fd4f01SNobuhiro Iwamatsu firmware { 30d4fd4f01SNobuhiro Iwamatsu zynqmp_firmware: zynqmp-firmware { 31d4fd4f01SNobuhiro Iwamatsu zynqmp_pcap: pcap { 32d4fd4f01SNobuhiro Iwamatsu compatible = "xlnx,zynqmp-pcap-fpga"; 33d4fd4f01SNobuhiro Iwamatsu }; 34d4fd4f01SNobuhiro Iwamatsu }; 35d4fd4f01SNobuhiro Iwamatsu }; 36d4fd4f01SNobuhiro Iwamatsu... 37