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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/input/linux-event-codes.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm845-wcd9340.dtsi"
20 /delete-node/ &rmtfs_mem;
29 stdout-path = "serial0:115200n8";
32 gpio-hall-sensor {
[all …]
H A Dsm8250-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/sound/qcom,q6afe.h>
10 #include <dt-bindings/sound/qcom,q6asm.h>
11 #include <dt-bindings/gpio/gpio.h>
20 compatible = "qcom,sm8250-mtp", "qcom,sm8250";
21 chassis-type = "handset";
27 wcd938x: audio-codec {
28 compatible = "qcom,wcd9380-codec";
[all …]
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
[all …]
H A Dsc7280-herobrine-audio-rt5682-3mic.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /* BOARD-SPECIFIC TOP LEVEL NODES */
13 compatible = "google,sc7280-herobrine";
14 model = "sc7280-rt5682-max98360a-3mic";
16 audio-routing = "VA DMIC0", "vdd-micb",
17 "VA DMIC1", "vdd-micb",
18 "VA DMIC2", "vdd-micb",
19 "VA DMIC3", "vdd-micb",
24 #address-cells = <1>;
25 #size-cells = <0>;
[all …]
H A Dmsm8996-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
14 #include <dt-bindings/sound/qcom,wcd9335.h>
23 compatible = "simple-battery";
25 constant-charge-current-max-microamp = <3000000>;
26 voltage-min-design-microvolt = <3400000>;
30 stdout-path = "serial1:115200n8";
[all …]
H A Dsdm845-db845c.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/sound/qcom,q6afe.h>
12 #include <dt-bindings/sound/qcom,q6asm.h>
14 #include "sdm845-wcd9340.dtsi"
21 qcom,msm-id = <341 0x20001>;
22 qcom,board-id = <8 0>;
[all …]
H A Dsm8550-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
20 compatible = "qcom,sm8550-mtp", "qcom,sm8550";
21 chassis-type = "handset";
27 wcd938x: audio-codec {
28 compatible = "qcom,wcd9385-codec";
30 pinctrl-names = "default";
31 pinctrl-0 = <&wcd_default>;
33 qcom,micbias1-microvolt = <1800000>;
[all …]
H A Dsdm850-samsung-w737.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 #include <dt-bindings/sound/qcom,q6afe.h>
15 #include <dt-bindings/sound/qcom,q6asm.h>
17 #include "sdm845-wcd9340.dtsi"
24 /delete-node/ &qseecom_mem;
[all …]
H A Dsm8550-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
21 compatible = "qcom,sm8550-qrd", "qcom,sm8550";
22 chassis-type = "handset";
28 wcd938x: audio-codec {
29 compatible = "qcom,wcd9385-codec";
31 pinctrl-names = "default";
32 pinctrl-0 = <&wcd_default>;
[all …]
H A Dqrb5165-rb5.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
19 compatible = "qcom,qrb5165-rb5", "qcom,sm8250";
20 qcom,msm-id = <455 0x20001>;
21 qcom,board-id = <11 3>;
29 stdout-path = "serial0:115200n8";
[all …]
H A Dsdm845-xiaomi-beryllium-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
7 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
8 #include <dt-bindings/sound/qcom,q6afe.h>
9 #include <dt-bindings/sound/qcom,q6asm.h>
11 #include "sdm845-wcd9340.dtsi"
19 /delete-node/ &tz_mem;
20 /delete-node/ &adsp_mem;
[all …]
H A Dsdm850-lenovo-yoga-c630.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/qcom,q6afe.h>
14 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm845-wcd9340.dtsi"
24 /delete-node/ &ipa_fw_mem;
25 /delete-node/ &ipa_gsi_mem;
[all …]
H A Dsm8450-hdk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
10 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
11 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 compatible = "qcom,sm8450-hdk", "qcom,sm8450";
25 chassis-type = "embedded";
[all …]
H A Dmsm8998-clamshell.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 vph_pwr: vph-pwr-regulator {
16 compatible = "regulator-fixed";
17 regulator-name = "vph_pwr";
18 regulator-always-on;
19 regulator-boot-on;
27 compatible = "qcom,wcn3990-bt";
29 vddio-supply = <&vreg_s4a_1p8>;
30 vddxo-supply = <&vreg_l7a_1p8>;
31 vddrf-supply = <&vreg_l17a_1p3>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-sopine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Based on sun50i-a64-pine64.dts, which is:
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 cpvdd-supply = <&reg_eldo1>;
16 cpu-supply = <&reg_dcdc2>;
20 cpu-supply = <&reg_dcdc2>;
24 cpu-supply = <&reg_dcdc2>;
28 cpu-supply = <&reg_dcdc2>;
[all …]
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Das3722_init.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2012-2016 Toradex, Inc.
8 #include <asm/arch-tegra/tegra_i2c.h>
11 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
17 writel(addr, &reg->cmd_addr0); in tegra_i2c_ll_write_addr()
18 writel(config, &reg->cnfg); in tegra_i2c_ll_write_addr()
25 writel(data, &reg->cmd_data1); in tegra_i2c_ll_write_data()
26 writel(config, &reg->cnfg); in tegra_i2c_ll_write_data()
40 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. in pmic_enable_cpu_vdd()
49 * First set VDD to 1.0V, then enable the VDD regulator. in pmic_enable_cpu_vdd()
[all …]
/openbmc/u-boot/drivers/power/
H A DKconfig19 ---help---
27 ---help---
36 ---help---
45 ---help---
54 ---help---
62 ---help---
69 ---help---
80 ---help---
83 generic 3.3V IO voltage for external devices like the lcd-panal and
85 save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
[all …]
/openbmc/u-boot/board/nvidia/venice2/
H A Das3722_init.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-tegra/tegra_i2c.h>
12 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
18 writel(addr, &reg->cmd_addr0); in tegra_i2c_ll_write_addr()
19 writel(config, &reg->cnfg); in tegra_i2c_ll_write_addr()
26 writel(data, &reg->cmd_data1); in tegra_i2c_ll_write_data()
27 writel(config, &reg->cnfg); in tegra_i2c_ll_write_data()
41 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. in pmic_enable_cpu_vdd()
50 * First set VDD to 1.0V, then enable the VDD regulator. in pmic_enable_cpu_vdd()
55 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. in pmic_enable_cpu_vdd()
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-bananapi-m2-plus-v1.2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
6 #include "sunxi-bananapi-m2-plus.dtsi"
11 * resistance on the CPU regulator's feedback pin.
13 reg_vdd_cpux: vdd-cpux {
14 compatible = "regulator-gpio";
15 regulator-name = "vdd-cpux";
16 regulator-type = "voltage";
17 regulator-boot-on;
18 regulator-always-on;
[all …]
H A Dsun7i-a20-icnova-a20.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // Copyright (C) 2023 In-Circuit GmbH
4 #include "sun7i-a20.dtsi"
5 #include "sunxi-common-regulators.dtsi"
7 #include <dt-bindings/interrupt-controller/irq.h>
10 cpu-supply = <&reg_dcdc2>;
14 pinctrl-names = "default";
15 pinctrl-0 = <&gmac_mii_pins>;
16 phy-handle = <&phy1>;
17 phy-mode = "mii";
[all …]
H A Dsun5i-a13-pocketbook-touch-lux-3.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "sun5i-a13.dtsi"
8 #include "sunxi-common-regulators.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pwm/pwm.h>
16 compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13";
26 compatible = "pwm-backlight";
[all …]
H A Dsun6i-a31s-sina31s-core.dtsi2 * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun6i-a31s.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
51 compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s";
59 cpu-supply = <&reg_dcdc3>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&mmc3_8bit_emmc_pins>;
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
11 #include <asm/arch-tegra/clk_rst.h>
12 #include <asm/arch-tegra/pmc.h>
13 #include <asm/arch-tegra/tegra_i2c.h>
14 #include "../cpu.h"
16 /* Tegra30-specific CPU init code */
21 writel(addr, &reg->cmd_addr0); in tegra_i2c_ll_write_addr()
22 writel(config, &reg->cnfg); in tegra_i2c_ll_write_addr()
29 writel(data, &reg->cmd_data1); in tegra_i2c_ll_write_data()
[all …]
/openbmc/linux/drivers/cpufreq/
H A Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
3 * CPU frequency scaling support for Armada 37xx platform.
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <linux/cpu.h>
24 #include "cpufreq-dt.h"
67 * On Armada 37xx the Power management manages 4 level of CPU load,
68 * each level can be associated with a CPU clock source, a CPU
69 * divider, a VDD level, etc...
124 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); in armada_37xx_cpu_freq_info_get()
138 /* Determine to which TBG clock is CPU connected */ in armada37xx_cpufreq_dvfs_setup()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun6i-a31s-sina31s-core.dtsi2 * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun6i-a31s.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
51 compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s";
59 cpu-supply = <&reg_dcdc3>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&mmc3_8bit_emmc_pins>;
[all …]

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