1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2f7dc4ac3STom Warren /*
3f7dc4ac3STom Warren * (C) Copyright 2013
4f7dc4ac3STom Warren * NVIDIA Corporation <www.nvidia.com>
5f7dc4ac3STom Warren */
6f7dc4ac3STom Warren
7f7dc4ac3STom Warren #include <common.h>
8f7dc4ac3STom Warren #include <asm/io.h>
9f7dc4ac3STom Warren #include <asm/arch-tegra/tegra_i2c.h>
10f7dc4ac3STom Warren #include "as3722_init.h"
11f7dc4ac3STom Warren
12f7dc4ac3STom Warren /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
13f7dc4ac3STom Warren
tegra_i2c_ll_write_addr(uint addr,uint config)14f7dc4ac3STom Warren void tegra_i2c_ll_write_addr(uint addr, uint config)
15f7dc4ac3STom Warren {
16f7dc4ac3STom Warren struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
17f7dc4ac3STom Warren
18f7dc4ac3STom Warren writel(addr, ®->cmd_addr0);
19f7dc4ac3STom Warren writel(config, ®->cnfg);
20f7dc4ac3STom Warren }
21f7dc4ac3STom Warren
tegra_i2c_ll_write_data(uint data,uint config)22f7dc4ac3STom Warren void tegra_i2c_ll_write_data(uint data, uint config)
23f7dc4ac3STom Warren {
24f7dc4ac3STom Warren struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
25f7dc4ac3STom Warren
26f7dc4ac3STom Warren writel(data, ®->cmd_data1);
27f7dc4ac3STom Warren writel(config, ®->cnfg);
28f7dc4ac3STom Warren }
29f7dc4ac3STom Warren
pmic_enable_cpu_vdd(void)30f7dc4ac3STom Warren void pmic_enable_cpu_vdd(void)
31f7dc4ac3STom Warren {
32f7dc4ac3STom Warren debug("%s entry\n", __func__);
33f7dc4ac3STom Warren
34b064c912SBibek Basu #ifdef AS3722_SD1VOLTAGE_DATA
35b064c912SBibek Basu /* Set up VDD_CORE, for boards where OTP is incorrect*/
36b064c912SBibek Basu debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
37b064c912SBibek Basu /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
38b064c912SBibek Basu tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
39b064c912SBibek Basu tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
40b064c912SBibek Basu /*
41b064c912SBibek Basu * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
42b064c912SBibek Basu * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
43b064c912SBibek Basu */
44b064c912SBibek Basu udelay(10 * 1000);
45b064c912SBibek Basu #endif
46f7dc4ac3STom Warren
47f7dc4ac3STom Warren debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
48f7dc4ac3STom Warren /*
49f7dc4ac3STom Warren * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
50f7dc4ac3STom Warren * First set VDD to 1.0V, then enable the VDD regulator.
51f7dc4ac3STom Warren */
52f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
53f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
54f7dc4ac3STom Warren /*
55f7dc4ac3STom Warren * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
56f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
57f7dc4ac3STom Warren */
58f7dc4ac3STom Warren udelay(10 * 1000);
59f7dc4ac3STom Warren
60f7dc4ac3STom Warren debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
61f7dc4ac3STom Warren /*
62f7dc4ac3STom Warren * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
63f7dc4ac3STom Warren * First set VDD to 1.0V, then enable the VDD regulator.
64f7dc4ac3STom Warren */
65f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
66f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
67f7dc4ac3STom Warren /*
68f7dc4ac3STom Warren * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
69f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
70f7dc4ac3STom Warren */
71f7dc4ac3STom Warren udelay(10 * 1000);
72f7dc4ac3STom Warren
73f7dc4ac3STom Warren debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
74f7dc4ac3STom Warren /*
75f7dc4ac3STom Warren * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
76f7dc4ac3STom Warren * First set VDD to 1.2V, then enable the VDD regulator.
77f7dc4ac3STom Warren */
78f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
79f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
80f7dc4ac3STom Warren /*
81f7dc4ac3STom Warren * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
82f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
83f7dc4ac3STom Warren */
84f7dc4ac3STom Warren udelay(10 * 1000);
85f7dc4ac3STom Warren
86f7dc4ac3STom Warren debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
87f7dc4ac3STom Warren /*
88f7dc4ac3STom Warren * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
89f7dc4ac3STom Warren * First set it to bypass 3.3V straight thru, then enable the regulator
90f7dc4ac3STom Warren *
91f7dc4ac3STom Warren * NOTE: We do this early because doing it later seems to hose the CPU
92f7dc4ac3STom Warren * power rail/partition startup. Need to debug.
93f7dc4ac3STom Warren */
94f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
95f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
96f7dc4ac3STom Warren /*
97f7dc4ac3STom Warren * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
98f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
99f7dc4ac3STom Warren */
100f7dc4ac3STom Warren udelay(10 * 1000);
101f7dc4ac3STom Warren }
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