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/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
27 * pre-determined set of performance points.
30 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
31 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
39 #include "analogbits-wrpll-cln28hpc.h"
41 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
44 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
47 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
50 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
53 /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
[all …]
/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
37 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]
/openbmc/linux/drivers/video/fbdev/kyro/
H A DSTG4000InitDevice.c69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
130 coreClock *= 100; /* in Hz */ in ProgramClock()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,plldig.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wen He <wen.he_1@nxp.com>
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
41 - compatible
[all …]
H A Dti,lmk04832.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
40 - description: PLL2 reference clock.
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/openbmc/linux/drivers/clk/
H A Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
74 * struct clk_si544_muldiv - Multiplier/divider settings
79 * If ls_div_bits is non-zero, hs_div must be even
80 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
93 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
117 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
131 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
135 settings->ls_div_bits = (reg[1] >> 4) & 0x07; in si544_get_muldiv()
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H A Dclk-plldig.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
33 /* Range of the VCO frequencies, in Hz */
37 /* Range of the output frequencies, in Hz */
70 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
76 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
86 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
91 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
98 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()
108 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()
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H A Dclk-lmk04832.c1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
22 /* 0x000 - 0x00d System Functions */
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
124 /* 0x146 - 0x14a CLKin Control */
134 /* 0x14b - 0x152 Holdover */
136 /* 0x153 - 0x15f PLL1 Configuration */
143 /* 0x160 - 0x16e PLL2 Configuration */
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H A Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
92 { 1, "security-gate", "secdiv", 0 },
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/openbmc/linux/drivers/media/dvb-frontends/
H A Dstb6100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 [STB6100_VCO] = "VCO",
125 .addr = state->config->tuner_address, in stb6100_read_regs()
131 rc = i2c_transfer(state->i2c, &msg, 1); in stb6100_read_regs()
134 state->config->tuner_address, rc); in stb6100_read_regs()
136 return -EREMOTEIO; in stb6100_read_regs()
141 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_regs()
153 .addr = state->config->tuner_address + reg, in stb6100_read_reg()
159 i2c_transfer(state->i2c, &msg, 1); in stb6100_read_reg()
163 return -EINVAL; in stb6100_read_reg()
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/openbmc/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
20 u32 cpu = readl(&mscmir->cpxtype); in get_cpu_rev()
30 u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0; in get_pllfreq() local
35 return -1; in get_pllfreq()
46 /* The formula for VCO is from TR manual, rev. D */ in get_pllfreq()
47 vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481); in get_pllfreq()
57 readl(DFS_DVPORTn(pll, selected_output - 1)); in get_pllfreq()
64 fout = vco / (dfs_mfi + (dfs_mfn / 256)); in get_pllfreq()
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/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3128-cru.h>
29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
44 /* All PLLs have same VCO and output frequency range restrictions. */ in rkclk_set_pll()
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
48 debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n", in rkclk_set_pll()
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H A Dclk_rk3036.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3036-cru.h>
27 ((input_rate) / (output_rate) - 1);
31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
37 #hz "Hz cannot be hit with PLL "\
48 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
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H A Dclk_rk3188.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
19 #include <dt-bindings/clock/rk3188-cru.h>
20 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
73 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
74 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
75 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
76 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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H A Dclk_rv1108.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Andy Yan <andy.yan@rock-chips.com>
9 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rv1108-cru.h>
31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
37 #hz "Hz cannot be hit with PLL "\
51 id = clk_id - 1; in rv1108_pll_id()
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H A Dclk_rk322x.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3228-cru.h>
28 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
30 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
32 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
33 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
34 #hz "Hz cannot be hit with PLL "\
45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
47 /* All PLLs have same VCO and output frequency range restrictions. */ in rkclk_set_pll()
[all …]
H A Dclk_rk3288.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
133 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
136 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
[all …]
H A Dclk_rk3368.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Andy Yan <andy.yan@rock-chips.com>
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
43 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
44 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
45 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
46 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
66 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dredboot.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 // include/asm-ppc/redboot.h
26 unsigned int bi_intfreq; /* Internal Freq, in Hz */
27 unsigned int bi_busfreq; /* Bus Freq, in Hz */
28 unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
29 unsigned int bi_brgfreq; /* BRG Freq, in Hz */
30 unsigned int bi_vco; /* VCO Out from PLL */
31 unsigned int bi_pci_freq; /* PCI Freq, in Hz */
H A Dppcboot.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
18 * include/asm-ppc/ppcboot.h
48 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
58 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
59 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
60 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
84 unsigned int bi_opbfreq; /* OB clock in Hz */
H A Dppcboot-hotfoot.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
11 * least-offensive solution. Please direct all flames to:
13 * Solomon Peachy <solomon@linux-wlan.com>
30 * include/asm-ppc/ppcboot.h
65 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
75 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
76 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
77 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
81 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dmax2165.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include "tuner-i2c.h"
38 msg.addr = priv->config->i2c_address; in max2165_write_reg()
43 ret = i2c_transfer(priv->i2c, &msg, 1); in max2165_write_reg()
49 return (ret != 1) ? -EIO : 0; in max2165_write_reg()
55 u8 dev_addr = priv->config->i2c_address; in max2165_read_reg()
64 ret = i2c_transfer(priv->i2c, msg, 2); in max2165_read_reg()
67 return -EIO; in max2165_read_reg()
104 priv->tf_ntch_low_cfg = dat[0] >> 4; in max2165_read_rom_table()
105 priv->tf_ntch_hi_cfg = dat[0] & 0x0F; in max2165_read_rom_table()
[all …]
/openbmc/linux/drivers/iio/frequency/
H A Dadf4371.c1 // SPDX-License-Identifier: GPL-2.0
63 #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
64 #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
65 #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
66 #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
67 #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
68 #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
70 #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
71 #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
73 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
86 * @returns 0 if ok, -1 on error (invalid clock id)
143 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
145 * @param reset 1 to assert reset, 0 to de-assert
154 * Warning: This function is only for use pre-relocation. Please use
168 * @param source source clock (0-15 depending on mux_bits)
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/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
35 adi,channel-spacing:
38 Channel spacing in Hz (influences MODULUS).
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