Lines Matching +full:vco +full:- +full:hz

1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
92 { 1, "security-gate", "secdiv", 0 },
93 { 2, "gmac0-gate", "ahb", 0 },
94 { 3, "gmac1-gate", "ahb", 0 },
95 { 4, "sata0-gate", "ahb", 0 },
96 { 5, "sata1-gate", "ahb", 0 },
97 { 6, "usb0-gate", "ahb", 0 },
98 { 7, "usb1-gate", "ahb", 0 },
99 { 8, "ide-gate", "ahb", 0 },
100 { 9, "pci-gate", "ahb", 0 },
105 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
110 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
111 { 12, "tvc-gate", "ahb", 0 },
112 { 13, "boot-gate", "apb", 0 },
125 regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val); in gemini_pci_recalc_rate()
146 return regmap_update_bits(pciclk->map, in gemini_pci_set_rate()
150 return regmap_update_bits(pciclk->map, in gemini_pci_set_rate()
153 return -EINVAL; in gemini_pci_set_rate()
160 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, in gemini_pci_enable()
169 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, in gemini_pci_disable()
178 regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val); in gemini_pci_is_enabled()
201 return ERR_PTR(-ENOMEM); in gemini_pci_clk_setup()
208 pciclk->map = map; in gemini_pci_clk_setup()
209 pciclk->hw.init = &init; in gemini_pci_clk_setup()
211 ret = clk_hw_register(NULL, &pciclk->hw); in gemini_pci_clk_setup()
217 return &pciclk->hw; in gemini_pci_clk_setup()
221 * This is a self-deasserting reset controller.
229 return regmap_write(gr->map, in gemini_reset()
253 ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val); in gemini_reset_status()
276 struct device *dev = &pdev->dev; in gemini_clk_probe()
277 struct device_node *np = dev->of_node; in gemini_clk_probe()
285 return -ENOMEM; in gemini_clk_probe()
298 gr->map = map; in gemini_clk_probe()
299 gr->rcdev.owner = THIS_MODULE; in gemini_clk_probe()
300 gr->rcdev.nr_resets = 32; in gemini_clk_probe()
301 gr->rcdev.ops = &gemini_reset_ops; in gemini_clk_probe()
302 gr->rcdev.of_node = np; in gemini_clk_probe()
304 ret = devm_reset_controller_register(dev, &gr->rcdev); in gemini_clk_probe()
310 /* RTC clock 32768 Hz */ in gemini_clk_probe()
312 gemini_clk_data->hws[GEMINI_CLK_RTC] = hw; in gemini_clk_probe()
321 gemini_clk_data->hws[GEMINI_CLK_CPU] = hw; in gemini_clk_probe()
341 gemini_clk_data->hws[GEMINI_CLK_GATES + i] = in gemini_clk_probe()
342 clk_hw_register_gate(NULL, gd->name, in gemini_clk_probe()
343 gd->parent_name, in gemini_clk_probe()
344 gd->flags, in gemini_clk_probe()
346 gd->bit_idx, in gemini_clk_probe()
352 * The TV Interface Controller has a 5-bit half divider register. in gemini_clk_probe()
362 gemini_clk_data->hws[GEMINI_CLK_TVC] = hw; in gemini_clk_probe()
366 gemini_clk_data->hws[GEMINI_CLK_PCI] = hw; in gemini_clk_probe()
370 gemini_clk_data->hws[GEMINI_CLK_UART] = hw; in gemini_clk_probe()
376 { .compatible = "cortina,gemini-syscon", },
383 .name = "gemini-clk",
405 gemini_clk_data->num = GEMINI_NUM_CLKS; in gemini_cc_init()
412 gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); in gemini_cc_init()
421 * but as this is an MMIO-backed regmap, subsequent regmap in gemini_cc_init()
442 /* VCO clock derived from the crystal */ in gemini_cc_init()
448 hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div); in gemini_cc_init()
450 /* The AHB clock is always 1/3 of the VCO */ in gemini_cc_init()
451 hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3); in gemini_cc_init()
452 gemini_clk_data->hws[GEMINI_CLK_AHB] = hw; in gemini_cc_init()
456 gemini_clk_data->hws[GEMINI_CLK_APB] = hw; in gemini_cc_init()
461 CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);