Lines Matching +full:vco +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Andy Yan <andy.yan@rock-chips.com>
9 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rv1108-cru.h>
31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
37 #hz "Hz cannot be hit with PLL "\
51 id = clk_id - 1; in rv1108_pll_id()
58 id = -1; in rv1108_pll_id()
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
71 /* All PLLs have same VCO and output frequency range restrictions. */ in rkclk_set_pll()
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
75 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
85 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
89 rk_setreg(&pll->con3, 1 << DSMPD_SHIFT); in rkclk_set_pll()
91 rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
95 (div->postdiv1 << POSTDIV1_SHIFT | in rkclk_set_pll()
96 div->postdiv2 << POSTDIV2_SHIFT | in rkclk_set_pll()
97 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
98 rk_clrsetreg(&pll->con2, FRACDIV_MASK, in rkclk_set_pll()
99 (div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
102 rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
105 while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT)) in rkclk_set_pll()
111 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
126 con3 = readl(&pll->con3); in rkclk_pll_get_rate()
129 con0 = readl(&pll->con0); in rkclk_pll_get_rate()
130 con1 = readl(&pll->con1); in rkclk_pll_get_rate()
145 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk()
158 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
170 u32 con = readl(&cru->clksel_con[27]); in rv1108_sfc_set_clk()
179 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
181 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, in rv1108_sfc_set_clk()
193 val = readl(&cru->clksel_con[22]); in rv1108_saradc_get_clk()
200 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_saradc_set_clk() argument
204 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
207 rk_clrsetreg(&cru->clksel_con[22], in rv1108_saradc_set_clk()
218 val = readl(&cru->clksel_con[28]); in rv1108_aclk_vio1_get_clk()
225 static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio1_set_clk() argument
229 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
232 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio1_set_clk()
244 val = readl(&cru->clksel_con[28]); in rv1108_aclk_vio0_get_clk()
251 static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio0_set_clk() argument
255 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
258 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio0_set_clk()
264 rk_clrsetreg(&cru->clksel_con[29], in rv1108_aclk_vio0_set_clk()
268 rk_clrsetreg(&cru->clksel_con[29], in rv1108_aclk_vio0_set_clk()
279 val = readl(&cru->clksel_con[32]); in rv1108_dclk_vop_get_clk()
286 static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_dclk_vop_set_clk() argument
290 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_dclk_vop_set_clk()
293 rk_clrsetreg(&cru->clksel_con[32], in rv1108_dclk_vop_set_clk()
308 val = readl(&cru->clksel_con[2]); in rv1108_aclk_bus_get_clk()
315 static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_bus_set_clk() argument
320 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_bus_set_clk()
323 rk_clrsetreg(&cru->clksel_con[2], in rv1108_aclk_bus_set_clk()
336 val = readl(&cru->clksel_con[23]); in rv1108_aclk_peri_get_clk()
348 val = readl(&cru->clksel_con[23]); in rv1108_hclk_peri_get_clk()
360 val = readl(&cru->clksel_con[23]); in rv1108_pclk_peri_get_clk()
367 static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_peri_set_clk() argument
372 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_peri_set_clk()
375 rk_clrsetreg(&cru->clksel_con[23], in rv1108_aclk_peri_set_clk()
383 static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_hclk_peri_set_clk() argument
388 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_hclk_peri_set_clk()
391 rk_clrsetreg(&cru->clksel_con[23], in rv1108_hclk_peri_set_clk()
398 static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_pclk_peri_set_clk() argument
403 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_pclk_peri_set_clk()
406 rk_clrsetreg(&cru->clksel_con[23], in rv1108_pclk_peri_set_clk()
419 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
424 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
429 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
434 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
440 return -EINVAL; in rv1108_i2c_get_clk()
446 static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz) in rv1108_i2c_set_clk() argument
451 src_clk_div = GPLL_HZ / hz; in rv1108_i2c_set_clk()
452 assert(src_clk_div - 1 <= 127); in rv1108_i2c_set_clk()
456 rk_clrsetreg(&cru->clksel_con[19], in rv1108_i2c_set_clk()
462 rk_clrsetreg(&cru->clksel_con[19], in rv1108_i2c_set_clk()
468 rk_clrsetreg(&cru->clksel_con[20], in rv1108_i2c_set_clk()
474 rk_clrsetreg(&cru->clksel_con[20], in rv1108_i2c_set_clk()
481 return -EINVAL; in rv1108_i2c_set_clk()
492 con = readl(&cru->clksel_con[26]); in rv1108_mmc_get_clk()
495 con = readl(&cru->clksel_con[25]); in rv1108_mmc_get_clk()
515 rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK, in rv1108_mmc_set_clk()
520 rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK, in rv1108_mmc_set_clk()
526 rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK, in rv1108_mmc_set_clk()
527 ((div - 1) << EMMC_CLK_DIV_SHIFT)); in rv1108_mmc_set_clk()
536 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); in rv1108_clk_get_rate()
538 switch (clk->id) { in rv1108_clk_get_rate()
540 return rkclk_pll_get_rate(priv->cru, clk->id); in rv1108_clk_get_rate()
542 return rv1108_saradc_get_clk(priv->cru); in rv1108_clk_get_rate()
544 return rv1108_aclk_vio0_get_clk(priv->cru); in rv1108_clk_get_rate()
546 return rv1108_aclk_vio1_get_clk(priv->cru); in rv1108_clk_get_rate()
548 return rv1108_dclk_vop_get_clk(priv->cru); in rv1108_clk_get_rate()
550 return rv1108_aclk_bus_get_clk(priv->cru); in rv1108_clk_get_rate()
552 return rv1108_aclk_peri_get_clk(priv->cru); in rv1108_clk_get_rate()
554 return rv1108_hclk_peri_get_clk(priv->cru); in rv1108_clk_get_rate()
556 return rv1108_pclk_peri_get_clk(priv->cru); in rv1108_clk_get_rate()
561 return rv1108_i2c_get_clk(priv->cru, clk->id); in rv1108_clk_get_rate()
565 return rv1108_mmc_get_clk(priv->cru); in rv1108_clk_get_rate()
567 return -ENOENT; in rv1108_clk_get_rate()
573 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); in rv1108_clk_set_rate()
576 switch (clk->id) { in rv1108_clk_set_rate()
578 new_rate = rv1108_mac_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
581 new_rate = rv1108_sfc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
584 new_rate = rv1108_saradc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
587 new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
590 new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
593 new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
596 new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
599 new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
602 new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
605 new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
611 new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate); in rv1108_clk_set_rate()
615 new_rate = rv1108_mmc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
618 return -ENOENT; in rv1108_clk_set_rate()
653 rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, in rkclk_init()
665 priv->cru = dev_read_addr_ptr(dev); in rv1108_clk_ofdata_to_platdata()
674 rkclk_init(priv->cru); in rv1108_clk_probe()
693 priv->glb_srst_fst_value = offsetof(struct rv1108_cru, in rv1108_clk_bind()
695 priv->glb_srst_snd_value = offsetof(struct rv1108_cru, in rv1108_clk_bind()
697 sys_child->priv = priv; in rv1108_clk_bind()
712 sf_priv->sf_reset_offset = offsetof(struct rv1108_cru, in rv1108_clk_bind()
714 sf_priv->sf_reset_num = 13; in rv1108_clk_bind()
715 sf_child->priv = sf_priv; in rv1108_clk_bind()
722 { .compatible = "rockchip,rv1108-cru" },