Lines Matching +full:vco +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3128-cru.h>
29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
44 /* All PLLs have same VCO and output frequency range restrictions. */ in rkclk_set_pll()
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
48 debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n", in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
57 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
59 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
61 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
62 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
63 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
64 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
67 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
70 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
88 printf("%s: the frequency can't be 0 Hz\n", __func__); in pll_para_config()
89 return -1; in pll_para_config()
102 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", in pll_para_config()
104 return -1; in pll_para_config()
107 div->postdiv1 = postdiv1; in pll_para_config()
108 div->postdiv2 = postdiv2; in pll_para_config()
117 diff_khz = vco_khz - fbdiv * fref_khz; in pll_para_config()
120 diff_khz = fref_khz - diff_khz; in pll_para_config()
127 div->refdiv = refdiv; in pll_para_config()
128 div->fbdiv = fbdiv; in pll_para_config()
132 printf("%s: Failed to match output frequency %u bestis %u Hz\n", in pll_para_config()
135 return -1; in pll_para_config()
146 /* pll enter slow-mode */ in rkclk_init()
147 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
159 * core hz : apll = 1:1 in rkclk_init()
161 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; in rkclk_init()
164 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()
167 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
172 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
181 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
184 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
187 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
190 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
195 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
204 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
215 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
223 /* PLL enter normal-mode */ in rkclk_init()
224 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
231 rk_clrsetreg(&cru->cru_clksel_con[2], in rkclk_init()
244 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
256 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
265 con = readl(&pll->con0); in rkclk_pll_get_rate()
268 con = readl(&pll->con1); in rkclk_pll_get_rate()
289 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
295 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
300 return -EINVAL; in rockchip_mmc_get_clk()
327 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
330 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
334 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
337 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
340 return -EINVAL; in rockchip_mmc_set_clk()
356 con = readl(&cru->cru_clksel_con[10]); in rk3128_peri_get_pclk()
361 return -EINVAL; in rk3128_peri_get_pclk()
367 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_peri_set_pclk() argument
371 src_clk_div = PERI_ACLK_HZ / hz; in rk3128_peri_set_pclk()
372 assert(src_clk_div - 1 < 4); in rk3128_peri_set_pclk()
380 rk_setreg(&cru->cru_clksel_con[10], in rk3128_peri_set_pclk()
381 ((src_clk_div - 1) << 12)); in rk3128_peri_set_pclk()
385 return -EINVAL; in rk3128_peri_set_pclk()
395 val = readl(&cru->cru_clksel_con[24]); in rk3128_saradc_get_clk()
402 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz) in rk3128_saradc_set_clk() argument
406 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
409 rk_clrsetreg(&cru->cru_clksel_con[24], in rk3128_saradc_set_clk()
416 static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_vop_set_clk() argument
421 src_clk_div = GPLL_HZ / hz; in rk3128_vop_set_clk()
422 assert(src_clk_div - 1 < 31); in rk3128_vop_set_clk()
426 rk_clrsetreg(&cru->cru_clksel_con[31], in rk3128_vop_set_clk()
429 (src_clk_div - 1) << VIO0_DIV_SHIFT); in rk3128_vop_set_clk()
432 rk_clrsetreg(&cru->cru_clksel_con[31], in rk3128_vop_set_clk()
435 (src_clk_div - 1) << VIO1_DIV_SHIFT); in rk3128_vop_set_clk()
438 if (pll_para_config(hz, &cpll_config)) in rk3128_vop_set_clk()
439 return -1; in rk3128_vop_set_clk()
442 rk_clrsetreg(&cru->cru_clksel_con[27], in rk3128_vop_set_clk()
445 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); in rk3128_vop_set_clk()
449 return -EINVAL; in rk3128_vop_set_clk()
452 return hz; in rk3128_vop_set_clk()
461 con = readl(&cru->cru_clksel_con[31]); in rk3128_vop_get_rate()
466 con = readl(&cru->cru_clksel_con[31]); in rk3128_vop_get_rate()
471 con = readl(&cru->cru_clksel_con[27]); in rk3128_vop_get_rate()
476 return -ENOENT; in rk3128_vop_get_rate()
483 struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); in rk3128_clk_get_rate()
485 switch (clk->id) { in rk3128_clk_get_rate()
487 return rkclk_pll_get_rate(priv->cru, clk->id); in rk3128_clk_get_rate()
493 return rk3128_peri_get_pclk(priv->cru, clk->id); in rk3128_clk_get_rate()
495 return rk3128_saradc_get_clk(priv->cru); in rk3128_clk_get_rate()
499 return rk3128_vop_get_rate(priv->cru, clk->id); in rk3128_clk_get_rate()
501 return -ENOENT; in rk3128_clk_get_rate()
507 struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); in rk3128_clk_set_rate()
510 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3128_clk_set_rate()
511 switch (clk->id) { in rk3128_clk_set_rate()
517 new_rate = rk3128_vop_set_clk(priv->cru, in rk3128_clk_set_rate()
518 clk->id, rate); in rk3128_clk_set_rate()
521 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, in rk3128_clk_set_rate()
522 clk->id, rate); in rk3128_clk_set_rate()
529 new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate); in rk3128_clk_set_rate()
532 new_rate = rk3128_saradc_set_clk(priv->cru, rate); in rk3128_clk_set_rate()
535 return -ENOENT; in rk3128_clk_set_rate()
550 priv->cru = dev_read_addr_ptr(dev); in rk3128_clk_ofdata_to_platdata()
559 rkclk_init(priv->cru); in rk3128_clk_probe()
577 priv->glb_srst_fst_value = offsetof(struct rk3128_cru, in rk3128_clk_bind()
579 priv->glb_srst_snd_value = offsetof(struct rk3128_cru, in rk3128_clk_bind()
581 sys_child->priv = priv; in rk3128_clk_bind()
588 { .compatible = "rockchip,rk3128-cru" },
589 { .compatible = "rockchip,rk3126-cru" },