Lines Matching +full:vco +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
133 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
136 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
148 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
149 /* All PLLs have same VCO and output frequency range restrictions. */ in rkclk_set_pll()
150 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
151 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
153 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", in rkclk_set_pll()
154 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
157 (div->no == 1 || !(div->no % 2))); in rkclk_set_pll()
160 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
162 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, in rkclk_set_pll()
163 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
164 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
165 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
170 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
176 unsigned int hz) in rkclk_configure_ddr() argument
186 switch (hz) { in rkclk_configure_ddr()
201 return -EINVAL; in rkclk_configure_ddr()
204 /* pll enter slow-mode */ in rkclk_configure_ddr()
205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
211 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) in rkclk_configure_ddr()
214 /* PLL enter normal-mode */ in rkclk_configure_ddr()
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
238 printf("%s: the frequency can not be 0 Hz\n", __func__); in pll_para_config()
239 return -EINVAL; in pll_para_config()
257 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", in pll_para_config()
259 return -1; in pll_para_config()
262 div->no = no; in pll_para_config()
275 diff_khz = vco_khz - nf * fref_khz; in pll_para_config()
278 diff_khz = fref_khz - diff_khz; in pll_para_config()
285 div->nr = nr; in pll_para_config()
286 div->nf = nf; in pll_para_config()
290 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", in pll_para_config()
292 return -EINVAL; in pll_para_config()
306 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { in rockchip_mac_set_clk()
310 u32 con = readl(&cru->cru_clksel_con[21]); in rockchip_mac_set_clk()
323 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
325 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, in rockchip_mac_set_clk()
347 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, in rockchip_vop_set_clk()
353 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) in rockchip_vop_set_clk()
358 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, in rockchip_vop_set_clk()
364 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, in rockchip_vop_set_clk()
365 (lcdc_div - 1) << 8 | 2 << 0); in rockchip_vop_set_clk()
368 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, in rockchip_vop_set_clk()
369 (lcdc_div - 1) << 8 | 2 << 6); in rockchip_vop_set_clk()
393 val = readl(&cru->cru_clksel_con[8]); in rockchip_i2s_get_clk()
415 &cru->cru_clksel_con[8]); in rockchip_i2s_set_clk()
427 /* pll enter slow-mode */ in rkclk_init()
428 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
438 while ((readl(&grf->soc_status[1]) & in rkclk_init()
447 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; in rkclk_init()
449 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; in rkclk_init()
453 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; in rkclk_init()
457 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
469 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
480 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
488 /* PLL enter normal-mode */ in rkclk_init()
489 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
497 /* pll enter slow-mode */ in rk3288_clk_configure_cpu()
498 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
504 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) in rk3288_clk_configure_cpu()
513 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3288_clk_configure_cpu()
524 rk_clrsetreg(&cru->cru_clksel_con[37], in rk3288_clk_configure_cpu()
531 /* PLL enter normal-mode */ in rk3288_clk_configure_cpu()
532 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
543 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
550 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
557 con = readl(&pll->con0); in rkclk_pll_get_rate()
560 con = readl(&pll->con1); in rkclk_pll_get_rate()
580 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
586 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
592 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
597 return -EINVAL; in rockchip_mmc_get_clk()
628 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
631 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
635 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
638 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
642 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
645 (src_clk_div - 1) << SDIO0_DIV_SHIFT); in rockchip_mmc_set_clk()
648 return -EINVAL; in rockchip_mmc_set_clk()
662 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
667 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
672 con = readl(&cru->cru_clksel_con[39]); in rockchip_spi_get_clk()
677 return -EINVAL; in rockchip_spi_get_clk()
690 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk()
694 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
700 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
706 rk_clrsetreg(&cru->cru_clksel_con[39], in rockchip_spi_set_clk()
712 return -EINVAL; in rockchip_spi_set_clk()
722 val = readl(&cru->cru_clksel_con[24]); in rockchip_saradc_get_clk()
729 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) in rockchip_saradc_set_clk() argument
733 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
736 rk_clrsetreg(&cru->cru_clksel_con[24], in rockchip_saradc_set_clk()
745 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rk3288_clk_get_rate()
748 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_get_rate()
749 switch (clk->id) { in rk3288_clk_get_rate()
751 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3288_clk_get_rate()
759 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
764 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
776 new_rate = rockchip_saradc_get_clk(priv->cru); in rk3288_clk_get_rate()
779 return -ENOENT; in rk3288_clk_get_rate()
787 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rk3288_clk_set_rate()
788 struct rk3288_cru *cru = priv->cru; in rk3288_clk_set_rate()
791 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_set_rate()
792 switch (clk->id) { in rk3288_clk_set_rate()
796 return -EINVAL; in rk3288_clk_set_rate()
797 rk3288_clk_configure_cpu(priv->cru, priv->grf); in rk3288_clk_set_rate()
801 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); in rk3288_clk_set_rate()
809 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); in rk3288_clk_set_rate()
814 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); in rk3288_clk_set_rate()
821 new_rate = rockchip_mac_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
825 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); in rk3288_clk_set_rate()
829 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); in rk3288_clk_set_rate()
832 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
834 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
843 assert((div - 1 < 64) && (div * rate == CPLL_HZ)); in rk3288_clk_set_rate()
845 switch (clk->id) { in rk3288_clk_set_rate()
847 rk_clrsetreg(&cru->cru_clksel_con[31], in rk3288_clk_set_rate()
849 0 << 6 | (div - 1) << 0); in rk3288_clk_set_rate()
852 rk_clrsetreg(&cru->cru_clksel_con[31], in rk3288_clk_set_rate()
854 0 << 14 | (div - 1) << 8); in rk3288_clk_set_rate()
862 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); in rk3288_clk_set_rate()
865 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
867 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
872 new_rate = rockchip_saradc_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
886 return -ENOENT; in rk3288_clk_set_rate()
894 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rk3288_gmac_set_parent()
895 struct rk3288_cru *cru = priv->cru; in rk3288_gmac_set_parent()
900 * If the requested parent is in the same clock-controller and in rk3288_gmac_set_parent()
904 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { in rk3288_gmac_set_parent()
906 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); in rk3288_gmac_set_parent()
911 * Otherwise, we need to check the clock-output-names of the in rk3288_gmac_set_parent()
914 ret = dev_read_string_index(parent->dev, "clock-output-names", in rk3288_gmac_set_parent()
915 parent->id, &clock_output_name); in rk3288_gmac_set_parent()
917 return -ENODATA; in rk3288_gmac_set_parent()
922 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, in rk3288_gmac_set_parent()
927 return -EINVAL; in rk3288_gmac_set_parent()
932 switch (clk->id) { in rk3288_clk_set_parent()
939 debug("%s: unsupported clk %ld\n", __func__, clk->id); in rk3288_clk_set_parent()
940 return -ENOENT; in rk3288_clk_set_parent()
945 switch (clk->id) { in rk3288_clk_enable()
961 debug("%s: unsupported clk %ld\n", __func__, clk->id); in rk3288_clk_enable()
962 return -ENOENT; in rk3288_clk_enable()
979 priv->cru = dev_read_addr_ptr(dev); in rk3288_clk_ofdata_to_platdata()
990 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3288_clk_probe()
991 if (IS_ERR(priv->grf)) in rk3288_clk_probe()
992 return PTR_ERR(priv->grf); in rk3288_clk_probe()
997 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3288_clk_probe()
1001 if (!(gd->flags & GD_FLG_RELOC)) { in rk3288_clk_probe()
1005 * Init clocks in U-Boot proper if the NPLL is runnning. This in rk3288_clk_probe()
1007 * we need to redo it. U-Boot's SPL does not set this clock. in rk3288_clk_probe()
1009 reg = readl(&priv->cru->cru_mode_con); in rk3288_clk_probe()
1016 rkclk_init(priv->cru, priv->grf); in rk3288_clk_probe()
1034 priv->glb_srst_fst_value = offsetof(struct rk3288_cru, in rk3288_clk_bind()
1036 priv->glb_srst_snd_value = offsetof(struct rk3288_cru, in rk3288_clk_bind()
1038 sys_child->priv = priv; in rk3288_clk_bind()
1052 { .compatible = "rockchip,rk3288-cru" },