Home
last modified time | relevance | path

Searched full:tmp (Results 1 – 25 of 4361) sorted by relevance

12345678910>>...175

/openbmc/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_run_64r6eb.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6eb
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6eb
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6eb
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6eb
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6eb
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6eb
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6eb
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6eb
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6eb
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6eb
[all …]
H A Dtest_msa_run_32r5eb.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5eb
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5eb
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5eb
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5eb
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5eb
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5eb
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5eb
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5eb
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5eb
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5eb
[all …]
H A Dtest_msa_run_64r6el.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6el
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6el
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6el
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6el
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6el
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6el
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6el
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6el
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6el
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6el
[all …]
H A Dtest_msa_run_32r5el.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5el
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5el
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5el
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5el
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5el
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5el
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5el
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5el
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5el
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5el
[all …]
/openbmc/linux/arch/loongarch/include/asm/
H A Dasmmacro.h42 .macro fpu_save_csr thread tmp
43 movfcsr2gr \tmp, fcsr0
44 stptr.w \tmp, \thread, THREAD_FCSR
47 andi \tmp, \tmp, FPU_CSR_TM
48 beqz \tmp, 1f
50 x86mftop \tmp
51 stptr.w \tmp, \thread, THREAD_FTOP
131 .macro fpu_save_double thread tmp
132 li.w \tmp, THREAD_FPR0
133 PTR_ADD \tmp, \tmp, \thread
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-ld4.c17 u32 tmp, clk_mode_upll, clk_mode_axosel; in upll_init() local
19 tmp = readl(SG_PINMON0); in upll_init()
20 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; in upll_init()
21 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; in upll_init()
24 tmp = readl(SC_UPLLCTRL); in upll_init()
25 tmp &= ~0x18000000; in upll_init()
26 writel(tmp, SC_UPLLCTRL); in upll_init()
32 tmp &= ~0x07ffffff; in upll_init()
33 tmp |= 0x0228f5c0; in upll_init()
36 tmp &= ~0x07ffffff; in upll_init()
[all …]
H A Dpll-pro4.c17 u32 tmp, clk_mode_axosel; in vpll_init() local
20 tmp = readl(SG_PINMON0); in vpll_init()
21 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; in vpll_init()
29 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
30 tmp |= 0x00000001; in vpll_init()
31 writel(tmp, SC_VPLL27ACTRL); in vpll_init()
32 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
33 tmp |= 0x00000001; in vpll_init()
34 writel(tmp, SC_VPLL27BCTRL); in vpll_init()
37 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
[all …]
/openbmc/openbmc-test-automation/ffdc/
H A Dffdc_config.yaml20 - "rm -rf /tmp/*BMC_* /tmp/PEL_* /tmp/pldm* /tmp/PLDM* /tmp/GUARD*
21 /tmp/fan_* /tmp/DEVTREE /tmp/bmcweb_*"
23 /tmp/OPENBMC_general.txt'
24 - "cat /etc/os-release >> /tmp/OPENBMC_general.txt"
26 /tmp/OPENBMC_general.txt'
27 - "cat /etc/timestamp >> /tmp/OPENBMC_general.txt"
29 /tmp/OPENBMC_general.txt'
30 - "uname -a >> /tmp/OPENBMC_general.txt"
32 /tmp/OPENBMC_general.txt'
33 - "cat /etc/timestamp >> /tmp/OPENBMC_general.txt"
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c156 uint32_t tmp; in gfxhub_v1_0_init_tlb_regs() local
159 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
163 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
165 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
167 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
169 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
171 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
176 uint32_t tmp; in gfxhub_v1_0_init_cache_regs() local
[all …]
H A Dgfxhub_v2_0.c188 uint32_t tmp; in gfxhub_v2_0_init_tlb_regs() local
191 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
202 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
207 uint32_t tmp; in gfxhub_v2_0_init_cache_regs() local
214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
[all …]
H A Dgfxhub_v3_0.c187 uint32_t tmp; in gfxhub_v3_0_init_tlb_regs() local
190 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_init_tlb_regs()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
202 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_init_tlb_regs()
207 uint32_t tmp; in gfxhub_v3_0_init_cache_regs() local
[all …]
H A Dgfxhub_v3_0_3.c192 uint32_t tmp; in gfxhub_v3_0_3_init_tlb_regs() local
195 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_3_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_3_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_3_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_3_init_tlb_regs()
204 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
207 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_3_init_tlb_regs()
212 uint32_t tmp; in gfxhub_v3_0_3_init_cache_regs() local
[all …]
H A Dmmhub_v3_0_2.c163 uint32_t tmp; in mmhub_v3_0_2_init_system_aperture_regs() local
197 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_2_init_system_aperture_regs()
198 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_2_init_system_aperture_regs()
200 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_2_init_system_aperture_regs()
205 uint32_t tmp; in mmhub_v3_0_2_init_tlb_regs() local
208 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_2_init_tlb_regs()
211 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_2_init_tlb_regs()
212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_2_init_tlb_regs()
214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_2_init_tlb_regs()
[all …]
H A Dmmhub_v3_0_1.c172 uint32_t tmp; in mmhub_v3_0_1_init_system_aperture_regs() local
204 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_1_init_system_aperture_regs()
205 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_1_init_system_aperture_regs()
207 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_1_init_system_aperture_regs()
212 uint32_t tmp; in mmhub_v3_0_1_init_tlb_regs() local
215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_1_init_tlb_regs()
218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_1_init_tlb_regs()
219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_1_init_tlb_regs()
221 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_1_init_tlb_regs()
[all …]
H A Dmmhub_v3_0.c170 uint32_t tmp; in mmhub_v3_0_init_system_aperture_regs() local
205 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_init_system_aperture_regs()
206 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_init_system_aperture_regs()
208 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_init_system_aperture_regs()
213 uint32_t tmp; in mmhub_v3_0_init_tlb_regs() local
216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_init_tlb_regs()
219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_init_tlb_regs()
220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_init_tlb_regs()
222 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_init_tlb_regs()
[all …]
H A Dmmhub_v2_3.c153 uint32_t tmp; in mmhub_v2_3_init_system_aperture_regs() local
179 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_3_init_system_aperture_regs()
180 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_3_init_system_aperture_regs()
182 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_3_init_system_aperture_regs()
187 uint32_t tmp; in mmhub_v2_3_init_tlb_regs() local
190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
192 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_3_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_3_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_3_init_tlb_regs()
[all …]
H A Dgfxhub_v1_2.c128 uint32_t tmp; in gfxhub_v1_2_xcc_init_system_aperture_regs() local
174 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2); in gfxhub_v1_2_xcc_init_system_aperture_regs()
175 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_2_xcc_init_system_aperture_regs()
177 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp); in gfxhub_v1_2_xcc_init_system_aperture_regs()
197 uint32_t tmp; in gfxhub_v1_2_xcc_init_tlb_regs() local
202 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_init_tlb_regs()
204 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
208 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
[all …]
H A Dmmhub_v2_0.c221 uint32_t tmp; in mmhub_v2_0_init_system_aperture_regs() local
249 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
250 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
252 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_0_init_system_aperture_regs()
257 uint32_t tmp; in mmhub_v2_0_init_tlb_regs() local
260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
262 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
263 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_0_init_tlb_regs()
264 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
266 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
[all …]
H A Dmmhub_v1_8.c129 uint32_t tmp, inst_mask; in mmhub_v1_8_init_system_aperture_regs() local
183 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_8_init_system_aperture_regs()
184 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_8_init_system_aperture_regs()
186 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_8_init_system_aperture_regs()
192 uint32_t tmp, inst_mask; in mmhub_v1_8_init_tlb_regs() local
198 tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_8_init_tlb_regs()
200 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, in mmhub_v1_8_init_tlb_regs()
202 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
204 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c95 u32 tmp; in fsl_serdes_init() local
115 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
116 tmp &= ~FSL_SRDSCR0_TXEQA_MASK; in fsl_serdes_init()
117 tmp |= FSL_SRDSCR0_TXEQA_SATA; in fsl_serdes_init()
118 tmp &= ~FSL_SRDSCR0_TXEQE_MASK; in fsl_serdes_init()
119 tmp |= FSL_SRDSCR0_TXEQE_SATA; in fsl_serdes_init()
120 out_be32(sd + FSL_SRDSCR0_OFFS, tmp); in fsl_serdes_init()
122 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
123 tmp &= ~FSL_SRDSCR1_LANEA_MASK; in fsl_serdes_init()
124 tmp &= ~FSL_SRDSCR1_LANEE_MASK; in fsl_serdes_init()
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
203 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
205 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
393 uint32_t tmp; in radeon_legacy_set_engine_clock() local
400 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
401 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
404 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
405 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
[all …]
H A Dvce_v2_0.c41 u32 tmp; in vce_v2_0_set_sw_cg() local
44 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
45 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
46 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
48 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
49 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
50 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
52 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
53 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
54 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
[all …]
/openbmc/linux/drivers/scsi/mvsas/
H A Dmv_64xx.c31 u32 tmp; in mvs_64xx_enable_xmt() local
33 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt()
35 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); in mvs_64xx_enable_xmt()
37 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_64xx_enable_xmt()
38 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
70 u32 reg, tmp; in mvs_64xx_stp_reset() local
81 tmp = reg; in mvs_64xx_stp_reset()
83 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
85 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
89 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c50 u32 tmp; in fsl_setup_serdes() local
55 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
56 tmp &= ~FSL_SRDSCR0_DPP_1V2; in fsl_setup_serdes()
57 out_be32(regs + FSL_SRDSCR0_OFFS, tmp); in fsl_setup_serdes()
60 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
61 tmp &= ~FSL_SRDSCR2_VDD_1V2; in fsl_setup_serdes()
62 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); in fsl_setup_serdes()
69 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
70 tmp |= FSL_SRDSRSTCTL_SATA_RESET; in fsl_setup_serdes()
71 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); in fsl_setup_serdes()
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_ssd1331.c133 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; in set_gamma() local
144 tmp[i] = acc; in set_gamma()
154 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], in set_gamma()
155 tmp[7], tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], in set_gamma()
156 tmp[14], tmp[15], tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], in set_gamma()
157 tmp[21], tmp[22], tmp[23], tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
158 tmp[28], tmp[29], tmp[30], tmp[31], tmp[32], tmp[33], tmp[34], in set_gamma()
159 tmp[35], tmp[36], tmp[37], tmp[38], tmp[39], tmp[40], tmp[41], in set_gamma()
160 tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47], tmp[48], in set_gamma()
161 tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55], in set_gamma()
[all …]

12345678910>>...175