50 	u32 tmp;  in fsl_setup_serdes()  local
55 		tmp = in_be32(regs + FSL_SRDSCR0_OFFS);  in fsl_setup_serdes()
56 		tmp &= ~FSL_SRDSCR0_DPP_1V2;  in fsl_setup_serdes()
57 		out_be32(regs + FSL_SRDSCR0_OFFS, tmp);  in fsl_setup_serdes()
60 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
61 		tmp &= ~FSL_SRDSCR2_VDD_1V2;  in fsl_setup_serdes()
62 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
69 		tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);  in fsl_setup_serdes()
70 		tmp |= FSL_SRDSRSTCTL_SATA_RESET;  in fsl_setup_serdes()
71 		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);  in fsl_setup_serdes()
73 		tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;  in fsl_setup_serdes()
74 		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);  in fsl_setup_serdes()
82 		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);  in fsl_setup_serdes()
83 		tmp &= ~FSL_SRDSCR1_PLLBW;  in fsl_setup_serdes()
84 		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);  in fsl_setup_serdes()
87 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
88 		tmp &= ~FSL_SRDSCR2_SEIC_MASK;  in fsl_setup_serdes()
89 		tmp |= FSL_SRDSCR2_SEIC_SATA;  in fsl_setup_serdes()
90 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
93 		tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |  in fsl_setup_serdes()
96 		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);  in fsl_setup_serdes()
99 		tmp = rfcks | FSL_SRDSCR4_PROT_SATA;  in fsl_setup_serdes()
100 		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);  in fsl_setup_serdes()
105 		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);  in fsl_setup_serdes()
106 		tmp |= FSL_SRDSCR1_PLLBW;  in fsl_setup_serdes()
107 		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);  in fsl_setup_serdes()
110 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
111 		tmp &= ~FSL_SRDSCR2_SEIC_MASK;  in fsl_setup_serdes()
112 		tmp |= FSL_SRDSCR2_SEIC_PEX;  in fsl_setup_serdes()
113 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
116 		tmp = FSL_SRDSCR3_SDFM_SATA_PEX;  in fsl_setup_serdes()
117 		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);  in fsl_setup_serdes()
120 		tmp = rfcks | FSL_SRDSCR4_PROT_PEX;  in fsl_setup_serdes()
122 			tmp |= FSL_SRDSCR4_PLANE_X2;  in fsl_setup_serdes()
123 		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);  in fsl_setup_serdes()
127 		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);  in fsl_setup_serdes()
128 		tmp &= ~FSL_SRDSCR1_PLLBW;  in fsl_setup_serdes()
129 		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);  in fsl_setup_serdes()
132 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
133 		tmp &= ~FSL_SRDSCR2_SEIC_MASK;  in fsl_setup_serdes()
134 		tmp |= FSL_SRDSCR2_SEIC_SGMII;  in fsl_setup_serdes()
135 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
141 		tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;  in fsl_setup_serdes()
142 		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);  in fsl_setup_serdes()
149 	tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);  in fsl_setup_serdes()
150 	tmp |= FSL_SRDSRSTCTL_RST;  in fsl_setup_serdes()
151 	out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);  in fsl_setup_serdes()