Lines Matching full:tmp
30 u32 tmp; in set_r5_halt_mode() local
32 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_halt_mode()
34 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
36 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
37 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_halt_mode()
40 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_halt_mode()
42 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
44 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
45 writel(tmp, &rpu_base->rpu1_cfg); in set_r5_halt_mode()
51 u32 tmp; in set_r5_tcm_mode() local
53 tmp = readl(&rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
55 tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; in set_r5_tcm_mode()
56 tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | in set_r5_tcm_mode()
59 tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; in set_r5_tcm_mode()
60 tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | in set_r5_tcm_mode()
64 writel(tmp, &rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
69 u32 tmp; in release_r5_reset() local
71 tmp = readl(&crlapb_base->rst_cpu_r5); in release_r5_reset()
72 tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK | in release_r5_reset()
77 tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK; in release_r5_reset()
79 writel(tmp, &crlapb_base->rst_cpu_r5); in release_r5_reset()
84 u32 tmp; in enable_clock_r5() local
86 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()
87 tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; in enable_clock_r5()
88 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()