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/openbmc/linux/drivers/gpu/drm/tegra/
H A Dmipi-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/phy/phy.h>
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20 v = (tmax - tmin) * percent; in linear_inter()
22 if (even && (v & 0x1)) in linear_inter()
23 return max_t(s32, min_result, v - 1); in linear_inter()
28 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
[all …]
H A Ddsi_phy_20nm.c1 // SPDX-License-Identifier: GPL-2.0-only
11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
16 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
18 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
20 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
25 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
27 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
29 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
29 #define CLK_SOURCE_EMC 0x19c
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
32 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
53 #define EMC_SRC_PLL_M 0
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/openbmc/u-boot/drivers/video/tegra124/
H A Ddisplay.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch-tegra/dc.h>
21 #include <dm/uclass-internal.h>
25 static int tegra_dc_calc_refresh(const struct display_timing *timing) in tegra_dc_calc_refresh() argument
28 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
30 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
31 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
32 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
33 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
35 return 0; in tegra_dc_calc_refresh()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_validation.c27 * This file owns timing validation against various link limitations. (ex.
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_tmds_output_pixel_clock_100hz() argument
41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
60 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; in dp_active_dongle_validate_timing()
62 switch (dpcd_caps->dongle_type) { in dp_active_dongle_validate_timing()
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/openbmc/u-boot/drivers/video/
H A Datmel_lcdfb.c1 // SPDX-License-Identifier: GPL-2.0+
32 struct display_timing timing; member
36 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
54 return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0)); in configuration_get_cmap()
60 *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03); in fb_put_word()
61 *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2); in fb_put_word()
75 for (i = 0; i < BMP_LOGO_COLORS; ++i) { in lcd_logo_set_cmap()
78 lut_entry = ((colreg & 0x000F) << 11) | in lcd_logo_set_cmap()
79 ((colreg & 0x00F0) << 2) | in lcd_logo_set_cmap()
80 ((colreg & 0x0F00) >> 7); in lcd_logo_set_cmap()
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
45 case 0x10: in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_vid.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
17 (e) && (e)->parent ? \
18 (e)->parent->base.id : -1, \
19 (e) && (e)->hw_intf ? \
20 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
23 (e) && (e)->parent ? \
24 (e)->parent->base.id : -1, \
25 (e) && (e)->hw_intf ? \
26 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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/openbmc/linux/drivers/video/fbdev/
H A Dgbefb.c4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
42 #define GBE_BASE 0x16000000 /* SGI O2 */
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
81 static int gbe_turned_on; /* 0 turned off, 1 turned on */
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
92 .xoffset = 0,
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/openbmc/linux/drivers/video/fbdev/via/
H A Dvia_modesetting.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
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/openbmc/linux/drivers/memory/tegra/
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
31 #define EMC_FBIO_CFG5 0x104
32 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
33 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
36 #define EMC_INTSTATUS 0x0
39 #define EMC_CFG 0xc
44 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
47 #define EMC_REFCTRL 0x20
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
42 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) in optc201_is_two_pixels_per_containter() argument
44 return optc1_is_two_pixels_per_containter(timing); in optc201_is_two_pixels_per_containter()
51 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc201_triplebuffer_lock()
52 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); in optc201_triplebuffer_lock()
53 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_lock()
55 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_lock()
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/openbmc/linux/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
14 #define AWG_MAX_ARG 0x3ff
34 u32 instruction = 0; in awg_generate_instr()
35 u32 mux = (mux_sel << 8) & 0x1ff; in awg_generate_instr()
36 u32 data_enable = (data_en << 9) & 0x2ff; in awg_generate_instr()
46 while (arg_tmp > 0) { in awg_generate_instr()
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddc_dsc.c52 /* Need to account for padding due to pixel-to-symbol packing
56 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
70 /* Symbols_per_HActive = HActive * bpp / (4 lanes * 32-bit symbol size) in apply_128b_132b_stream_overhead()
73 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
88 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
91 uint32_t bits_per_channel = 0; in dc_bandwidth_in_kbps_from_timing()
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
95 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c34 #include <subdev/bios/timing.h>
71 #define T(t) cfg->timing_10_##t
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
77 struct nvkm_device *device = subdev->device; in nv50_ram_timing_calc()
81 cur2 = nvkm_rd32(device, 0x100228); in nv50_ram_timing_calc()
82 cur4 = nvkm_rd32(device, 0x100230); in nv50_ram_timing_calc()
83 cur7 = nvkm_rd32(device, 0x10023c); in nv50_ram_timing_calc()
84 cur8 = nvkm_rd32(device, 0x100240); in nv50_ram_timing_calc()
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/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
13 #define MEM_MODE_MASK GENMASK(2, 0)
16 #define NOT_FOUND 0xff
19 /* 0x0 */
21 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
23 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
25 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
27 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
30 /* 0x80 */
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator_v.c42 tg->ctx->logger
45 * DCE11 Timing Generator Implementation
56 * Set MASTER_UPDATE_MODE to 0 in dce110_timing_generator_v_enable_crtc()
61 value = 0; in dce110_timing_generator_v_enable_crtc()
62 set_reg_field_value(value, 0, in dce110_timing_generator_v_enable_crtc()
64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
68 value = 0; in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
71 value = 0; in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
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/openbmc/u-boot/common/
H A Dedid.c1 // SPDX-License-Identifier: GPL-2.0+
21 if ((edid_info == NULL) || (edid_info->version == 0)) in edid_check_info()
22 return -1; in edid_check_info()
24 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) in edid_check_info()
25 return -1; in edid_check_info()
27 if (edid_info->version == 0xff && edid_info->revision == 0xff) in edid_check_info()
28 return -1; in edid_check_info()
30 return 0; in edid_check_info()
35 u8 checksum = 0; in edid_check_checksum()
38 for (i = 0; i < 128; i++) in edid_check_checksum()
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/openbmc/u-boot/board/xilinx/zynqmp/
H A Dtap_delays.c1 // SPDX-License-Identifier: GPL-2.0
11 #define SD_DLL_CTRL 0xFF180358
12 #define SD_ITAP_DLY 0xFF180314
13 #define SD_OTAP_DLY 0xFF180318
14 #define SD0_DLL_RST_MASK 0x00000004
15 #define SD0_DLL_RST 0x00000004
16 #define SD1_DLL_RST_MASK 0x00040000
17 #define SD1_DLL_RST 0x00040000
18 #define SD0_ITAPCHGWIN_MASK 0x00000200
19 #define SD0_ITAPCHGWIN 0x00000200
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/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
11 u32 mstr ; /* 0x0 Master*/
12 u32 stat; /* 0x4 Operating Mode Status*/
13 u8 reserved008[0x10 - 0x8];
14 u32 mrctrl0; /* 0x10 Control 0.*/
15 u32 mrctrl1; /* 0x14 Control 1*/
16 u32 mrstat; /* 0x18 Status*/
17 u32 reserved01c; /* 0x1c */
18 u32 derateen; /* 0x20 Temperature Derate Enable*/
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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/openbmc/linux/drivers/ata/
H A Dpata_triflex.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_triflex.c - Compaq PATA for new ATA layer
15 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
36 * triflex_prereset - probe begin
46 { 0x80, 1, 0x01, 0x01 }, in triflex_prereset()
47 { 0x80, 1, 0x02, 0x02 } in triflex_prereset()
50 struct ata_port *ap = link->ap; in triflex_prereset()
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_prereset()
53 if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no])) in triflex_prereset()
54 return -ENOENT; in triflex_prereset()
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dxenon_sdhci.c1 // SPDX-License-Identifier: GPL-2.0
8 * Date: 2016-8-24
13 * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
26 /* Register Offset of SD Host Controller SOCP self-defined register */
27 #define SDHC_SYS_CFG_INFO 0x0104
29 #define SLOT_TYPE_EMMC_MASK 0xFF
31 #define SLOT_TYPE_SD_SDIO_MMC_MASK 0xFF
33 #define NR_SUPPORTED_SLOT_MASK 0x7
35 #define SDHC_SYS_OP_CTRL 0x0108
38 #define SLOT_ENABLE_SHIFT 0
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/openbmc/u-boot/drivers/video/stm32/
H A Dstm32_ltdc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
16 #include <dm/device-internal.h>
22 struct display_timing timing; member
30 #define LTDC_IDR 0x00 /* IDentification */
31 #define LTDC_LCR 0x04 /* Layer Count */
32 #define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
33 #define LTDC_BPCR 0x0C /* Back Porch Configuration */
34 #define LTDC_AWCR 0x10 /* Active Width Configuration */
35 #define LTDC_TWCR 0x14 /* Total Width Configuration */
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