Lines Matching +full:timing +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
16 #include <dm/device-internal.h>
22 struct display_timing timing; member
30 #define LTDC_IDR 0x00 /* IDentification */
31 #define LTDC_LCR 0x04 /* Layer Count */
32 #define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
33 #define LTDC_BPCR 0x0C /* Back Porch Configuration */
34 #define LTDC_AWCR 0x10 /* Active Width Configuration */
35 #define LTDC_TWCR 0x14 /* Total Width Configuration */
36 #define LTDC_GCR 0x18 /* Global Control */
37 #define LTDC_GC1R 0x1C /* Global Configuration 1 */
38 #define LTDC_GC2R 0x20 /* Global Configuration 2 */
39 #define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
40 #define LTDC_GACR 0x28 /* GAmma Correction */
41 #define LTDC_BCCR 0x2C /* Background Color Configuration */
42 #define LTDC_IER 0x34 /* Interrupt Enable */
43 #define LTDC_ISR 0x38 /* Interrupt Status */
44 #define LTDC_ICR 0x3C /* Interrupt Clear */
45 #define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
46 #define LTDC_CPSR 0x44 /* Current Position Status */
47 #define LTDC_CDSR 0x48 /* Current Display Status */
50 #define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */
51 #define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */
52 #define LTDC_L1CR 0x84 /* L1 Control */
53 #define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */
54 #define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */
55 #define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */
56 #define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */
57 #define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */
58 #define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */
59 #define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */
60 #define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */
61 #define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */
62 #define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */
63 #define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */
64 #define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */
65 #define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */
66 #define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */
67 #define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */
68 #define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */
71 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
74 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
77 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
80 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
83 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
85 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
86 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
87 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
88 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
90 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
100 #define GC1R_TP BIT(25) /* Timing Programmable */
107 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
108 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
109 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
110 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
114 #define SRCR_IMR BIT(0) /* IMmediate Reload */
117 #define LXCR_LEN BIT(0) /* Layer ENable */
119 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
121 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
124 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
127 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
129 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
131 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
134 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
137 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
139 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
140 #define BF1_CA 0x400 /* Constant Alpha */
141 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
142 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
145 PF_ARGB8888 = 0,
183 debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf); in stm32_ltdc_get_pixel_format()
208 setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR); in stm32_ltdc_enable()
209 setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN); in stm32_ltdc_enable()
214 void __iomem *regs = priv->regs; in stm32_ltdc_set_mode()
215 struct display_timing *timing = &priv->timing; in stm32_ltdc_set_mode() local
221 hsync = timing->hsync_len.typ - 1; in stm32_ltdc_set_mode()
222 vsync = timing->vsync_len.typ - 1; in stm32_ltdc_set_mode()
223 acc_hbp = hsync + timing->hback_porch.typ; in stm32_ltdc_set_mode()
224 acc_vbp = vsync + timing->vback_porch.typ; in stm32_ltdc_set_mode()
225 acc_act_w = acc_hbp + timing->hactive.typ; in stm32_ltdc_set_mode()
226 acc_act_h = acc_vbp + timing->vactive.typ; in stm32_ltdc_set_mode()
227 total_w = acc_act_w + timing->hfront_porch.typ; in stm32_ltdc_set_mode()
228 total_h = acc_act_h + timing->vfront_porch.typ; in stm32_ltdc_set_mode()
249 val = 0; in stm32_ltdc_set_mode()
250 debug("%s: timing->flags 0x%08x\n", __func__, timing->flags); in stm32_ltdc_set_mode()
251 if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH) in stm32_ltdc_set_mode()
253 if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH) in stm32_ltdc_set_mode()
255 if (timing->flags & DISPLAY_FLAGS_DE_HIGH) in stm32_ltdc_set_mode()
257 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) in stm32_ltdc_set_mode()
263 writel(priv->bg_col_argb, priv->regs + LTDC_BCCR); in stm32_ltdc_set_mode()
268 void __iomem *regs = priv->regs; in stm32_ltdc_set_layer1()
276 x0 = priv->crop_x; in stm32_ltdc_set_layer1()
277 x1 = priv->crop_x + priv->crop_w - 1; in stm32_ltdc_set_layer1()
278 y0 = priv->crop_y; in stm32_ltdc_set_layer1()
279 y1 = priv->crop_y + priv->crop_h - 1; in stm32_ltdc_set_layer1()
294 writel(priv->bg_col_argb, regs + LTDC_L1DCCR); in stm32_ltdc_set_layer1()
297 bpp = VNBITS(priv->l2bpp); in stm32_ltdc_set_layer1()
298 pitch_in_bytes = priv->crop_w * (bpp >> 3); in stm32_ltdc_set_layer1()
300 line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1; in stm32_ltdc_set_layer1()
305 format = stm32_ltdc_get_pixel_format(priv->l2bpp); in stm32_ltdc_set_layer1()
309 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha); in stm32_ltdc_set_layer1()
312 /* Manage hw-specific capabilities */ in stm32_ltdc_set_layer1()
319 clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h); in stm32_ltdc_set_layer1()
325 setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN); in stm32_ltdc_set_layer1()
338 priv->regs = (void *)dev_read_addr(dev); in stm32_ltdc_probe()
339 if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { in stm32_ltdc_probe()
341 return -EINVAL; in stm32_ltdc_probe()
344 ret = clk_get_by_index(dev, 0, &pclk); in stm32_ltdc_probe()
357 ret = reset_get_by_index(dev, 0, &rst); in stm32_ltdc_probe()
360 return -ENODEV; in stm32_ltdc_probe()
375 __func__, panel->name, ret); in stm32_ltdc_probe()
379 ret = fdtdec_decode_display_timing(gd->fdt_blob, in stm32_ltdc_probe()
380 dev_of_offset(dev), 0, in stm32_ltdc_probe()
381 &priv->timing); in stm32_ltdc_probe()
383 debug("%s: decode display timing error %d\n", in stm32_ltdc_probe()
385 return -EINVAL; in stm32_ltdc_probe()
388 rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ); in stm32_ltdc_probe()
389 if (rate < 0) { in stm32_ltdc_probe()
391 __func__, priv->timing.pixelclock.typ, rate); in stm32_ltdc_probe()
396 priv->timing.pixelclock.typ, rate); in stm32_ltdc_probe()
398 /* TODO Below parameters are hard-coded for the moment... */ in stm32_ltdc_probe()
399 priv->l2bpp = VIDEO_BPP16; in stm32_ltdc_probe()
400 priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */ in stm32_ltdc_probe()
401 priv->crop_x = 0; in stm32_ltdc_probe()
402 priv->crop_y = 0; in stm32_ltdc_probe()
403 priv->crop_w = priv->timing.hactive.typ; in stm32_ltdc_probe()
404 priv->crop_h = priv->timing.vactive.typ; in stm32_ltdc_probe()
405 priv->alpha = 0xFF; in stm32_ltdc_probe()
407 debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__, in stm32_ltdc_probe()
408 priv->timing.hactive.typ, priv->timing.vactive.typ, in stm32_ltdc_probe()
409 VNBITS(priv->l2bpp), uc_plat->base); in stm32_ltdc_probe()
410 debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__, in stm32_ltdc_probe()
411 priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h, in stm32_ltdc_probe()
412 priv->bg_col_argb, priv->alpha); in stm32_ltdc_probe()
416 stm32_ltdc_set_layer1(priv, uc_plat->base); in stm32_ltdc_probe()
419 uc_priv->xsize = priv->timing.hactive.typ; in stm32_ltdc_probe()
420 uc_priv->ysize = priv->timing.vactive.typ; in stm32_ltdc_probe()
421 uc_priv->bpix = priv->l2bpp; in stm32_ltdc_probe()
425 return 0; in stm32_ltdc_probe()
432 uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES * in stm32_ltdc_bind()
435 debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size); in stm32_ltdc_bind()
437 return 0; in stm32_ltdc_bind()
441 { .compatible = "st,stm32-ltdc" },