1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
239cf4804SStelian Pop /*
339cf4804SStelian Pop * Driver for AT91/AT32 LCD Controller
439cf4804SStelian Pop *
539cf4804SStelian Pop * Copyright (C) 2007 Atmel Corporation
639cf4804SStelian Pop */
739cf4804SStelian Pop
839cf4804SStelian Pop #include <common.h>
99dc89a05SSimon Glass #include <atmel_lcd.h>
109dc89a05SSimon Glass #include <dm.h>
11d63ec26aSSimon Glass #include <fdtdec.h>
129dc89a05SSimon Glass #include <video.h>
1339cf4804SStelian Pop #include <asm/io.h>
1439cf4804SStelian Pop #include <asm/arch/gpio.h>
1539cf4804SStelian Pop #include <asm/arch/clk.h>
1639cf4804SStelian Pop #include <lcd.h>
170b29a896SNikita Kiryanov #include <bmp_layout.h>
1839cf4804SStelian Pop #include <atmel_lcdc.h>
1939cf4804SStelian Pop
209dc89a05SSimon Glass DECLARE_GLOBAL_DATA_PTR;
219dc89a05SSimon Glass
229dc89a05SSimon Glass #ifdef CONFIG_DM_VIDEO
239dc89a05SSimon Glass enum {
249dc89a05SSimon Glass /* Maximum LCD size we support */
259dc89a05SSimon Glass LCD_MAX_WIDTH = 1366,
269dc89a05SSimon Glass LCD_MAX_HEIGHT = 768,
279dc89a05SSimon Glass LCD_MAX_LOG2_BPP = VIDEO_BPP16,
289dc89a05SSimon Glass };
299dc89a05SSimon Glass #endif
309dc89a05SSimon Glass
319dc89a05SSimon Glass struct atmel_fb_priv {
329dc89a05SSimon Glass struct display_timing timing;
339dc89a05SSimon Glass };
349dc89a05SSimon Glass
3539cf4804SStelian Pop /* configurable parameters */
3639cf4804SStelian Pop #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
3739cf4804SStelian Pop #define ATMEL_LCDC_DMA_BURST_LEN 8
386bbced67SMark Jackson #ifndef ATMEL_LCDC_GUARD_TIME
396bbced67SMark Jackson #define ATMEL_LCDC_GUARD_TIME 1
406bbced67SMark Jackson #endif
4139cf4804SStelian Pop
42c6941e12SBo Shen #if defined(CONFIG_AT91SAM9263)
4339cf4804SStelian Pop #define ATMEL_LCDC_FIFO_SIZE 2048
4439cf4804SStelian Pop #else
4539cf4804SStelian Pop #define ATMEL_LCDC_FIFO_SIZE 512
4639cf4804SStelian Pop #endif
4739cf4804SStelian Pop
4839cf4804SStelian Pop #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
4939cf4804SStelian Pop #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
5039cf4804SStelian Pop
519dc89a05SSimon Glass #ifndef CONFIG_DM_VIDEO
configuration_get_cmap(void)5238b55087SNikita Kiryanov ushort *configuration_get_cmap(void)
5338b55087SNikita Kiryanov {
5438b55087SNikita Kiryanov return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
5538b55087SNikita Kiryanov }
5638b55087SNikita Kiryanov
57b3d12e9bSNikita Kiryanov #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
fb_put_word(uchar ** fb,uchar ** from)58b3d12e9bSNikita Kiryanov void fb_put_word(uchar **fb, uchar **from)
59b3d12e9bSNikita Kiryanov {
60b3d12e9bSNikita Kiryanov *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
61b3d12e9bSNikita Kiryanov *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
62b3d12e9bSNikita Kiryanov *from += 2;
63b3d12e9bSNikita Kiryanov }
64b3d12e9bSNikita Kiryanov #endif
65b3d12e9bSNikita Kiryanov
66a02e9481SNikita Kiryanov #ifdef CONFIG_LCD_LOGO
67a02e9481SNikita Kiryanov #include <bmp_logo.h>
lcd_logo_set_cmap(void)68a02e9481SNikita Kiryanov void lcd_logo_set_cmap(void)
69a02e9481SNikita Kiryanov {
70a02e9481SNikita Kiryanov int i;
71a02e9481SNikita Kiryanov uint lut_entry;
72a02e9481SNikita Kiryanov ushort colreg;
73a02e9481SNikita Kiryanov uint *cmap = (uint *)configuration_get_cmap();
74a02e9481SNikita Kiryanov
75a02e9481SNikita Kiryanov for (i = 0; i < BMP_LOGO_COLORS; ++i) {
76a02e9481SNikita Kiryanov colreg = bmp_logo_palette[i];
77a02e9481SNikita Kiryanov #ifdef CONFIG_ATMEL_LCD_BGR555
78a02e9481SNikita Kiryanov lut_entry = ((colreg & 0x000F) << 11) |
79a02e9481SNikita Kiryanov ((colreg & 0x00F0) << 2) |
80a02e9481SNikita Kiryanov ((colreg & 0x0F00) >> 7);
81a02e9481SNikita Kiryanov #else
82a02e9481SNikita Kiryanov lut_entry = ((colreg & 0x000F) << 1) |
83a02e9481SNikita Kiryanov ((colreg & 0x00F0) << 3) |
84a02e9481SNikita Kiryanov ((colreg & 0x0F00) << 4);
85a02e9481SNikita Kiryanov #endif
86a02e9481SNikita Kiryanov *(cmap + BMP_LOGO_OFFSET) = lut_entry;
87a02e9481SNikita Kiryanov cmap++;
88a02e9481SNikita Kiryanov }
89a02e9481SNikita Kiryanov }
90a02e9481SNikita Kiryanov #endif
91a02e9481SNikita Kiryanov
lcd_setcolreg(ushort regno,ushort red,ushort green,ushort blue)9239cf4804SStelian Pop void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
9339cf4804SStelian Pop {
9439cf4804SStelian Pop #if defined(CONFIG_ATMEL_LCD_BGR555)
9539cf4804SStelian Pop lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
9639cf4804SStelian Pop (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
9739cf4804SStelian Pop #else
9839cf4804SStelian Pop lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
9939cf4804SStelian Pop (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
10039cf4804SStelian Pop #endif
10139cf4804SStelian Pop }
10239cf4804SStelian Pop
lcd_set_cmap(struct bmp_image * bmp,unsigned colors)1031c3dbe56SSimon Glass void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
1040b29a896SNikita Kiryanov {
1050b29a896SNikita Kiryanov int i;
1060b29a896SNikita Kiryanov
1070b29a896SNikita Kiryanov for (i = 0; i < colors; ++i) {
1081c3dbe56SSimon Glass struct bmp_color_table_entry cte = bmp->color_table[i];
1090b29a896SNikita Kiryanov lcd_setcolreg(i, cte.red, cte.green, cte.blue);
1100b29a896SNikita Kiryanov }
1110b29a896SNikita Kiryanov }
1129dc89a05SSimon Glass #endif
1130b29a896SNikita Kiryanov
atmel_fb_init(ulong addr,struct display_timing * timing,int bpix,bool tft,bool cont_pol_low,ulong lcdbase)114d63ec26aSSimon Glass static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
115d63ec26aSSimon Glass bool tft, bool cont_pol_low, ulong lcdbase)
11639cf4804SStelian Pop {
11739cf4804SStelian Pop unsigned long value;
118d63ec26aSSimon Glass void *reg = (void *)addr;
11939cf4804SStelian Pop
12039cf4804SStelian Pop /* Turn off the LCD controller and the DMA controller */
121d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_PWRCON,
1226bbced67SMark Jackson ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
12339cf4804SStelian Pop
12439cf4804SStelian Pop /* Wait for the LCDC core to become idle */
125d63ec26aSSimon Glass while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
12639cf4804SStelian Pop udelay(10);
12739cf4804SStelian Pop
128d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
12939cf4804SStelian Pop
13039cf4804SStelian Pop /* Reset LCDC DMA */
131d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
13239cf4804SStelian Pop
13339cf4804SStelian Pop /* ...set frame size and burst length = 8 words (?) */
134d63ec26aSSimon Glass value = (timing->hactive.typ * timing->vactive.typ *
135d63ec26aSSimon Glass (1 << bpix)) / 32;
13639cf4804SStelian Pop value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
137d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
13839cf4804SStelian Pop
13939cf4804SStelian Pop /* Set pixel clock */
140d63ec26aSSimon Glass value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
141d63ec26aSSimon Glass if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
14239cf4804SStelian Pop value++;
14339cf4804SStelian Pop value = (value / 2) - 1;
14439cf4804SStelian Pop
14539cf4804SStelian Pop if (!value) {
146d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
14739cf4804SStelian Pop } else
148d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
14939cf4804SStelian Pop value << ATMEL_LCDC_CLKVAL_OFFSET);
15039cf4804SStelian Pop
15139cf4804SStelian Pop /* Initialize control register 2 */
15239cf4804SStelian Pop value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
153d63ec26aSSimon Glass if (tft)
15439cf4804SStelian Pop value |= ATMEL_LCDC_DISTYPE_TFT;
15539cf4804SStelian Pop
156d63ec26aSSimon Glass if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
157d63ec26aSSimon Glass value |= ATMEL_LCDC_INVLINE_INVERTED;
158d63ec26aSSimon Glass if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
159d63ec26aSSimon Glass value |= ATMEL_LCDC_INVFRAME_INVERTED;
160d63ec26aSSimon Glass value |= bpix << 5;
161d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
16239cf4804SStelian Pop
16339cf4804SStelian Pop /* Vertical timing */
164d63ec26aSSimon Glass value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
165d63ec26aSSimon Glass value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
166d63ec26aSSimon Glass value |= timing->vfront_porch.typ;
167d63ec26aSSimon Glass /* Magic! (Datasheet says "Bit 31 must be written to 1") */
168d63ec26aSSimon Glass value |= 1U << 31;
169d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
17039cf4804SStelian Pop
17139cf4804SStelian Pop /* Horizontal timing */
172d63ec26aSSimon Glass value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
173d63ec26aSSimon Glass value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
174d63ec26aSSimon Glass value |= (timing->hback_porch.typ - 1);
175d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
17639cf4804SStelian Pop
17739cf4804SStelian Pop /* Display size */
178d63ec26aSSimon Glass value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
179d63ec26aSSimon Glass value |= timing->vactive.typ - 1;
180d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
18139cf4804SStelian Pop
18239cf4804SStelian Pop /* FIFO Threshold: Use formula from data sheet */
18339cf4804SStelian Pop value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
184d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
18539cf4804SStelian Pop
18639cf4804SStelian Pop /* Toggle LCD_MODE every frame */
187d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
18839cf4804SStelian Pop
18939cf4804SStelian Pop /* Disable all interrupts */
190d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
19139cf4804SStelian Pop
19239cf4804SStelian Pop /* Set contrast */
19339cf4804SStelian Pop value = ATMEL_LCDC_PS_DIV8 |
19439cf4804SStelian Pop ATMEL_LCDC_ENA_PWMENABLE;
195d63ec26aSSimon Glass if (!cont_pol_low)
196cdfcedbfSAlexander Stein value |= ATMEL_LCDC_POL_POSITIVE;
197d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
198d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
19939cf4804SStelian Pop
20039cf4804SStelian Pop /* Set framebuffer DMA base address and pixel offset */
201d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
20239cf4804SStelian Pop
203d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
204d63ec26aSSimon Glass lcdc_writel(reg, ATMEL_LCDC_PWRCON,
2056bbced67SMark Jackson (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
20639cf4804SStelian Pop }
20739cf4804SStelian Pop
2089dc89a05SSimon Glass #ifndef CONFIG_DM_VIDEO
lcd_ctrl_init(void * lcdbase)209d63ec26aSSimon Glass void lcd_ctrl_init(void *lcdbase)
210d63ec26aSSimon Glass {
211d63ec26aSSimon Glass struct display_timing timing;
212d63ec26aSSimon Glass
213d63ec26aSSimon Glass timing.flags = 0;
214d63ec26aSSimon Glass if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
215d63ec26aSSimon Glass timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
216d63ec26aSSimon Glass if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
217d63ec26aSSimon Glass timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
218d63ec26aSSimon Glass timing.pixelclock.typ = panel_info.vl_clk;
219d63ec26aSSimon Glass
220d63ec26aSSimon Glass timing.hactive.typ = panel_info.vl_col;
221d63ec26aSSimon Glass timing.hfront_porch.typ = panel_info.vl_right_margin;
222d63ec26aSSimon Glass timing.hback_porch.typ = panel_info.vl_left_margin;
223d63ec26aSSimon Glass timing.hsync_len.typ = panel_info.vl_hsync_len;
224d63ec26aSSimon Glass
225d63ec26aSSimon Glass timing.vactive.typ = panel_info.vl_row;
226d63ec26aSSimon Glass timing.vfront_porch.typ = panel_info.vl_clk;
227d63ec26aSSimon Glass timing.vback_porch.typ = panel_info.vl_clk;
228d63ec26aSSimon Glass timing.vsync_len.typ = panel_info.vl_clk;
229d63ec26aSSimon Glass
230d63ec26aSSimon Glass atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
231d63ec26aSSimon Glass panel_info.vl_tft, panel_info.vl_cont_pol_low,
232d63ec26aSSimon Glass (ulong)lcdbase);
233d63ec26aSSimon Glass }
234d63ec26aSSimon Glass
calc_fbsize(void)23539cf4804SStelian Pop ulong calc_fbsize(void)
23639cf4804SStelian Pop {
23739cf4804SStelian Pop return ((panel_info.vl_col * panel_info.vl_row *
23839cf4804SStelian Pop NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
23939cf4804SStelian Pop }
2409dc89a05SSimon Glass #endif
2419dc89a05SSimon Glass
2429dc89a05SSimon Glass #ifdef CONFIG_DM_VIDEO
atmel_fb_lcd_probe(struct udevice * dev)2439dc89a05SSimon Glass static int atmel_fb_lcd_probe(struct udevice *dev)
2449dc89a05SSimon Glass {
2459dc89a05SSimon Glass struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
2469dc89a05SSimon Glass struct video_priv *uc_priv = dev_get_uclass_priv(dev);
2479dc89a05SSimon Glass struct atmel_fb_priv *priv = dev_get_priv(dev);
2489dc89a05SSimon Glass struct display_timing *timing = &priv->timing;
2499dc89a05SSimon Glass
2509dc89a05SSimon Glass /*
2519dc89a05SSimon Glass * For now some values are hard-coded. We could use the device tree
2529dc89a05SSimon Glass * bindings in simple-framebuffer.txt to specify the format/bpp and
2539dc89a05SSimon Glass * some Atmel-specific binding for tft and cont_pol_low.
2549dc89a05SSimon Glass */
2559dc89a05SSimon Glass atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
2569dc89a05SSimon Glass uc_plat->base);
2579dc89a05SSimon Glass uc_priv->xsize = timing->hactive.typ;
2589dc89a05SSimon Glass uc_priv->ysize = timing->vactive.typ;
2599dc89a05SSimon Glass uc_priv->bpix = VIDEO_BPP16;
2609dc89a05SSimon Glass video_set_flush_dcache(dev, true);
2619dc89a05SSimon Glass debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
2629dc89a05SSimon Glass uc_plat->size, uc_priv->xsize, uc_priv->ysize);
2639dc89a05SSimon Glass
2649dc89a05SSimon Glass return 0;
2659dc89a05SSimon Glass }
2669dc89a05SSimon Glass
atmel_fb_ofdata_to_platdata(struct udevice * dev)2679dc89a05SSimon Glass static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
2689dc89a05SSimon Glass {
2699dc89a05SSimon Glass struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
2709dc89a05SSimon Glass struct atmel_fb_priv *priv = dev_get_priv(dev);
2719dc89a05SSimon Glass struct display_timing *timing = &priv->timing;
2729dc89a05SSimon Glass const void *blob = gd->fdt_blob;
2739dc89a05SSimon Glass
274e160f7d4SSimon Glass if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
2759dc89a05SSimon Glass plat->timing_index, timing)) {
2769dc89a05SSimon Glass debug("%s: Failed to decode display timing\n", __func__);
2779dc89a05SSimon Glass return -EINVAL;
2789dc89a05SSimon Glass }
2799dc89a05SSimon Glass
2809dc89a05SSimon Glass return 0;
2819dc89a05SSimon Glass }
2829dc89a05SSimon Glass
atmel_fb_lcd_bind(struct udevice * dev)2839dc89a05SSimon Glass static int atmel_fb_lcd_bind(struct udevice *dev)
2849dc89a05SSimon Glass {
2859dc89a05SSimon Glass struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
2869dc89a05SSimon Glass
2879dc89a05SSimon Glass uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
2889dc89a05SSimon Glass (1 << VIDEO_BPP16) / 8;
2899dc89a05SSimon Glass debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
2909dc89a05SSimon Glass
2919dc89a05SSimon Glass return 0;
2929dc89a05SSimon Glass }
2939dc89a05SSimon Glass
2949dc89a05SSimon Glass static const struct udevice_id atmel_fb_lcd_ids[] = {
2959dc89a05SSimon Glass { .compatible = "atmel,at91sam9g45-lcdc" },
2969dc89a05SSimon Glass { }
2979dc89a05SSimon Glass };
2989dc89a05SSimon Glass
2999dc89a05SSimon Glass U_BOOT_DRIVER(atmel_fb) = {
3009dc89a05SSimon Glass .name = "atmel_fb",
3019dc89a05SSimon Glass .id = UCLASS_VIDEO,
3029dc89a05SSimon Glass .of_match = atmel_fb_lcd_ids,
3039dc89a05SSimon Glass .bind = atmel_fb_lcd_bind,
3049dc89a05SSimon Glass .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
3059dc89a05SSimon Glass .probe = atmel_fb_lcd_probe,
3069dc89a05SSimon Glass .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
3079dc89a05SSimon Glass .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
3089dc89a05SSimon Glass };
3099dc89a05SSimon Glass #endif
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