Lines Matching +full:timing +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
13 #define MEM_MODE_MASK GENMASK(2, 0)
16 #define NOT_FOUND 0xff
19 /* 0x0 */
21 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
23 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
25 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
27 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
30 /* 0x80 */
33 u32 pmem; /* Common memory space timing register */
34 u32 patt; /* Attribute memory space timing registers */
39 /* 0x104 */
40 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
42 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
44 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
46 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
49 /* 0x140 */
52 u32 sdtr1; /* SDRAM Timing register 1 */
53 u32 sdtr2; /* SDRAM Timing register 2 */
55 u32 sdrtr; /* SDRAM Refresh timing register */
74 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
77 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
78 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
79 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
83 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
87 #define FMC_SDCMR_MODE_NORMAL 0
104 while (regs->sdsr & FMC_SDSR_BUSY) \
106 } while (0)
153 #define SDRAM_MODE_BL_SHIFT 0
155 #define SDRAM_MODE_BL 0
161 struct stm32_sdram_timing *timing; in stm32_sdram_init() local
162 struct stm32_fmc_regs *regs = params->base; in stm32_sdram_init()
169 if (params->family == STM32H7_FMC) in stm32_sdram_init()
170 clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); in stm32_sdram_init()
172 for (i = 0; i < params->no_sdram_banks; i++) { in stm32_sdram_init()
173 control = params->bank_params[i].sdram_control; in stm32_sdram_init()
174 timing = params->bank_params[i].sdram_timing; in stm32_sdram_init()
175 target_bank = params->bank_params[i].target_bank; in stm32_sdram_init()
176 ref_count = params->bank_params[i].sdram_ref_count; in stm32_sdram_init()
178 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT in stm32_sdram_init()
179 | control->cas_latency << FMC_SDCR_CAS_SHIFT in stm32_sdram_init()
180 | control->no_banks << FMC_SDCR_NB_SHIFT in stm32_sdram_init()
181 | control->memory_width << FMC_SDCR_MWID_SHIFT in stm32_sdram_init()
182 | control->no_rows << FMC_SDCR_NR_SHIFT in stm32_sdram_init()
183 | control->no_columns << FMC_SDCR_NC_SHIFT in stm32_sdram_init()
184 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT in stm32_sdram_init()
185 | control->rd_burst << FMC_SDCR_RBURST_SHIFT, in stm32_sdram_init()
186 ®s->sdcr1); in stm32_sdram_init()
189 writel(control->cas_latency << FMC_SDCR_CAS_SHIFT in stm32_sdram_init()
190 | control->no_banks << FMC_SDCR_NB_SHIFT in stm32_sdram_init()
191 | control->memory_width << FMC_SDCR_MWID_SHIFT in stm32_sdram_init()
192 | control->no_rows << FMC_SDCR_NR_SHIFT in stm32_sdram_init()
193 | control->no_columns << FMC_SDCR_NC_SHIFT, in stm32_sdram_init()
194 ®s->sdcr2); in stm32_sdram_init()
196 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
197 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
198 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
199 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
200 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
201 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
202 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
203 ®s->sdtr1); in stm32_sdram_init()
206 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
207 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
208 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
209 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
210 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
211 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
212 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
213 ®s->sdtr2); in stm32_sdram_init()
220 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); in stm32_sdram_init()
221 udelay(200); /* 200 us delay, page 10, "Power-Up" */ in stm32_sdram_init()
224 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); in stm32_sdram_init()
229 ®s->sdcmr); in stm32_sdram_init()
234 | control->cas_latency << SDRAM_MODE_CAS_SHIFT) in stm32_sdram_init()
236 ®s->sdcmr); in stm32_sdram_init()
240 writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); in stm32_sdram_init()
244 writel(ref_count << 1, ®s->sdrtr); in stm32_sdram_init()
248 if (params->family == STM32H7_FMC) in stm32_sdram_init()
249 setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); in stm32_sdram_init()
251 return 0; in stm32_sdram_init()
264 u8 bank = 0; in stm32_fmc_ofdata_to_platdata()
267 ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, in stm32_fmc_ofdata_to_platdata()
299 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
302 bank_params = ¶ms->bank_params[bank]; in stm32_fmc_ofdata_to_platdata()
304 (long unsigned int *)&bank_params->target_bank); in stm32_fmc_ofdata_to_platdata()
306 if (bank_params->target_bank >= MAX_SDRAM_BANK) { in stm32_fmc_ofdata_to_platdata()
307 pr_err("Found bank %d , but only bank 0 and 1 are supported", in stm32_fmc_ofdata_to_platdata()
308 bank_params->target_bank); in stm32_fmc_ofdata_to_platdata()
309 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
312 debug("Find bank %s %u\n", bank_name, bank_params->target_bank); in stm32_fmc_ofdata_to_platdata()
314 params->bank_params[bank].sdram_control = in stm32_fmc_ofdata_to_platdata()
317 "st,sdram-control", in stm32_fmc_ofdata_to_platdata()
320 if (!params->bank_params[bank].sdram_control) { in stm32_fmc_ofdata_to_platdata()
321 pr_err("st,sdram-control not found for %s", in stm32_fmc_ofdata_to_platdata()
323 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
327 params->bank_params[bank].sdram_timing = in stm32_fmc_ofdata_to_platdata()
330 "st,sdram-timing", in stm32_fmc_ofdata_to_platdata()
333 if (!params->bank_params[bank].sdram_timing) { in stm32_fmc_ofdata_to_platdata()
334 pr_err("st,sdram-timing not found for %s", in stm32_fmc_ofdata_to_platdata()
336 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
340 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, in stm32_fmc_ofdata_to_platdata()
341 "st,sdram-refcount", 8196); in stm32_fmc_ofdata_to_platdata()
345 params->no_sdram_banks = bank; in stm32_fmc_ofdata_to_platdata()
346 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); in stm32_fmc_ofdata_to_platdata()
348 return 0; in stm32_fmc_ofdata_to_platdata()
359 return -EINVAL; in stm32_fmc_probe()
361 params->base = (struct stm32_fmc_regs *)addr; in stm32_fmc_probe()
362 params->family = dev_get_driver_data(dev); in stm32_fmc_probe()
367 ret = clk_get_by_index(dev, 0, &clk); in stm32_fmc_probe()
368 if (ret < 0) in stm32_fmc_probe()
382 return 0; in stm32_fmc_probe()
387 return 0; in stm32_fmc_get_info()
395 { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
396 { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },