1 // SPDX-License-Identifier: GPL-2.0
8  * Date:	2016-8-24
13  * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
26 /* Register Offset of SD Host Controller SOCP self-defined register */
27 #define SDHC_SYS_CFG_INFO			0x0104
29 #define SLOT_TYPE_EMMC_MASK			0xFF
31 #define SLOT_TYPE_SD_SDIO_MMC_MASK		0xFF
33 #define NR_SUPPORTED_SLOT_MASK			0x7
35 #define SDHC_SYS_OP_CTRL			0x0108
38 #define SLOT_ENABLE_SHIFT			0
40 #define SDHC_SYS_EXT_OP_CTRL			0x010C
43 #define SDHC_SLOT_RETUNING_REQ_CTRL		0x0144
45 #define RETUNING_COMPATIBLE			0x1
48 #define XENON_SDHCI_CTRL_HS200			0x5
49 #define XENON_SDHCI_CTRL_HS400			0x6
51 #define EMMC_PHY_REG_BASE			0x170
58 #define WAIT_CYCLE_BEFORE_USING_MASK		0xf
60 #define FC_SYNC_EN_DURATION_MASK		0xf
62 #define FC_SYNC_RST_EN_DURATION_MASK		0xf
64 #define FC_SYNC_RST_DURATION_MASK		0xf
65 #define FC_SYNC_RST_DURATION_SHIFT		0
67 #define EMMC_PHY_FUNC_CONTROL			(EMMC_PHY_REG_BASE + 0x4)
70 #define DQ_DDR_MODE_MASK			0xff
73 #define EMMC_PHY_PAD_CONTROL			(EMMC_PHY_REG_BASE + 0x8)
75 #define REC_EN_MASK				0xf
83 #define EMMC_PHY_PAD_CONTROL1			(EMMC_PHY_REG_BASE + 0xc)
88 #define EMMC5_1_FC_DQ_PD			0xff
89 #define EMMC5_1_FC_DQ_PU			(0xff << 16)
91 #define SDHCI_RETUNE_EVT_INTSIG			0x00001000
93 /* Hyperion only have one slot 0 */
94 #define XENON_MMC_SLOT_ID_HYPERION		0
96 #define MMC_TIMING_LEGACY	0
123 	u8 timing;  member
133 	struct xenon_sdhci_priv *priv = host->mmc->priv;  in xenon_mmc_phy_init()
134 	u32 clock = priv->clock;  in xenon_mmc_phy_init()
141 	if ((priv->timing == MMC_TIMING_UHS_SDR50) ||  in xenon_mmc_phy_init()
142 	    (priv->timing == MMC_TIMING_UHS_SDR25) ||  in xenon_mmc_phy_init()
143 	    (priv->timing == MMC_TIMING_UHS_SDR12) ||  in xenon_mmc_phy_init()
144 	    (priv->timing == MMC_TIMING_SD_HS) ||  in xenon_mmc_phy_init()
145 	    (priv->timing == MMC_TIMING_LEGACY))  in xenon_mmc_phy_init()
152 	while (time--) {  in xenon_mmc_phy_init()
160 	if (time <= 0) {  in xenon_mmc_phy_init()
162 		return -ETIMEDOUT;  in xenon_mmc_phy_init()
170 	if (clock == 0) {  in xenon_mmc_phy_init()
178 	while (time--) {  in xenon_mmc_phy_init()
188 	if (time <= 0) {  in xenon_mmc_phy_init()
190 		return -ETIMEDOUT;  in xenon_mmc_phy_init()
193 	return 0;  in xenon_mmc_phy_init()
196 #define ARMADA_3700_SOC_PAD_1_8V	0x1
197 #define ARMADA_3700_SOC_PAD_3_3V	0x0
201 	struct xenon_sdhci_priv *priv = host->mmc->priv;  in armada_3700_soc_pad_voltage_set()
203 	if (priv->pad_type == SOC_PAD_FIXED_1_8V)  in armada_3700_soc_pad_voltage_set()
204 		writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);  in armada_3700_soc_pad_voltage_set()
205 	else if (priv->pad_type == SOC_PAD_SD)  in armada_3700_soc_pad_voltage_set()
206 		writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);  in armada_3700_soc_pad_voltage_set()
211 	struct xenon_sdhci_priv *priv = host->mmc->priv;  in xenon_mmc_phy_set()
227 	 * If timing belongs to high speed, set bit[17] of  in xenon_mmc_phy_set()
230 	if ((priv->timing == MMC_TIMING_MMC_HS400) ||  in xenon_mmc_phy_set()
231 	    (priv->timing == MMC_TIMING_MMC_HS200) ||  in xenon_mmc_phy_set()
232 	    (priv->timing == MMC_TIMING_UHS_SDR50) ||  in xenon_mmc_phy_set()
233 	    (priv->timing == MMC_TIMING_UHS_SDR104) ||  in xenon_mmc_phy_set()
234 	    (priv->timing == MMC_TIMING_UHS_DDR50) ||  in xenon_mmc_phy_set()
235 	    (priv->timing == MMC_TIMING_UHS_SDR25) ||  in xenon_mmc_phy_set()
236 	    (priv->timing == MMC_TIMING_MMC_DDR52)) {  in xenon_mmc_phy_set()
251 	if (host->mmc->ddr_mode) {  in xenon_mmc_phy_set()
307 	/* Clear the Re-Tuning Request functionality */  in xenon_mmc_disable_tuning()
312 	/* Clear the Re-tuning Event Signal Enable */  in xenon_mmc_disable_tuning()
331 	struct xenon_sdhci_priv *priv = host->mmc->priv;  in xenon_sdhci_set_ios_post()
332 	uint speed = host->mmc->tran_speed;  in xenon_sdhci_set_ios_post()
333 	int pwr_18v = 0;  in xenon_sdhci_set_ios_post()
339 	/* Set timing variable according to the configured speed */  in xenon_sdhci_set_ios_post()
340 	if (IS_SD(host->mmc)) {  in xenon_sdhci_set_ios_post()
343 			if (host->mmc->ddr_mode)  in xenon_sdhci_set_ios_post()
344 				priv->timing = MMC_TIMING_UHS_DDR50;  in xenon_sdhci_set_ios_post()
346 				priv->timing = MMC_TIMING_UHS_SDR25;  in xenon_sdhci_set_ios_post()
348 				priv->timing = MMC_TIMING_UHS_SDR50;  in xenon_sdhci_set_ios_post()
351 				priv->timing = MMC_TIMING_LEGACY;  in xenon_sdhci_set_ios_post()
353 				priv->timing = MMC_TIMING_SD_HS;  in xenon_sdhci_set_ios_post()
357 		if (host->mmc->ddr_mode)  in xenon_sdhci_set_ios_post()
358 			priv->timing = MMC_TIMING_MMC_DDR52;  in xenon_sdhci_set_ios_post()
360 			priv->timing = MMC_TIMING_LEGACY;  in xenon_sdhci_set_ios_post()
362 			priv->timing = MMC_TIMING_MMC_HS;  in xenon_sdhci_set_ios_post()
365 	/* Re-init the PHY */  in xenon_sdhci_set_ios_post()
382 	host->mmc = &plat->mmc;  in xenon_sdhci_probe()
383 	host->mmc->priv = host;  in xenon_sdhci_probe()
384 	host->mmc->dev = dev;  in xenon_sdhci_probe()
385 	upriv->mmc = host->mmc;  in xenon_sdhci_probe()
388 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;  in xenon_sdhci_probe()
390 	/* Set default timing */  in xenon_sdhci_probe()
391 	priv->timing = MMC_TIMING_LEGACY;  in xenon_sdhci_probe()
403 	if (priv->pad_ctrl_reg)  in xenon_sdhci_probe()
406 	host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;  in xenon_sdhci_probe()
407 	switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",  in xenon_sdhci_probe()
410 		host->host_caps |= MMC_MODE_8BIT;  in xenon_sdhci_probe()
413 		host->host_caps |= MMC_MODE_4BIT;  in xenon_sdhci_probe()
418 		printf("Invalid \"bus-width\" value\n");  in xenon_sdhci_probe()
419 		return -EINVAL;  in xenon_sdhci_probe()
422 	host->ops = &xenon_sdhci_ops;  in xenon_sdhci_probe()
424 	host->max_clk = XENON_MMC_MAX_CLK;  in xenon_sdhci_probe()
425 	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);  in xenon_sdhci_probe()
453 	host->name = dev->name;  in xenon_sdhci_ofdata_to_platdata()
454 	host->ioaddr = (void *)devfdt_get_addr(dev);  in xenon_sdhci_ofdata_to_platdata()
456 	if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))  in xenon_sdhci_ofdata_to_platdata()
457 		priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);  in xenon_sdhci_ofdata_to_platdata()
459 	name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",  in xenon_sdhci_ofdata_to_platdata()
462 		if (0 == strncmp(name, "sd", 2)) {  in xenon_sdhci_ofdata_to_platdata()
463 			priv->pad_type = SOC_PAD_SD;  in xenon_sdhci_ofdata_to_platdata()
464 		} else if (0 == strncmp(name, "fixed-1-8v", 10)) {  in xenon_sdhci_ofdata_to_platdata()
465 			priv->pad_type = SOC_PAD_FIXED_1_8V;  in xenon_sdhci_ofdata_to_platdata()
468 			return -EINVAL;  in xenon_sdhci_ofdata_to_platdata()
472 	return 0;  in xenon_sdhci_ofdata_to_platdata()
479 	return sdhci_bind(dev, &plat->mmc, &plat->cfg);  in xenon_sdhci_bind()
483 	{ .compatible = "marvell,armada-8k-sdhci",},
484 	{ .compatible = "marvell,armada-3700-sdhci",},