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/openbmc/linux/arch/powerpc/boot/
H A Dpq2.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "fsl-soc.h"
21 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
22 6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
25 /* Get various clocks from crystal frequency.
26 * Returns zero on failure and non-zero on success.
29 u32 *timebase, u32 *brgfreq) in pq2_get_clocks() argument
55 if (timebase) in pq2_get_clocks()
56 *timebase = busclk / 4; in pq2_get_clocks()
75 void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq) in pq2_set_clocks() argument
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H A Dtreeboot-akebono.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright 2002-2005 MontaVista Software Inc.
77 /* Fixup the SD timeout frequency */ in ibm_akebono_fixups()
80 /* Disable SD high-speed mode (which seems to be broken) */ in ibm_akebono_fixups()
88 setprop(emac, "local-mac-address", in ibm_akebono_fixups()
98 const u32 *timebase; in platform_init() local
102 userdata[USERDATA_LEN - 1] = '\0'; in platform_init()
104 for (i = 0; i < userdata_len - 15; i++) { in platform_init()
105 if (strncmp(&userdata[i], "local-mac-addr=", 15) == 0) { in platform_init()
106 if (i > 0 && userdata[i - 1] != ' ') { in platform_init()
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H A Dsimpleboot.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * The simple platform -- for booting when firmware doesn't supply a device
28 const u32 *na, *ns, *reg, *timebase; in platform_init() local
36 /* Find the #address-cells and #size-cells properties */ in platform_init()
40 na = fdt_getprop(_dtb_start, node, "#address-cells", &size); in platform_init()
42 fatal("Cannot find #address-cells property"); in platform_init()
43 ns = fdt_getprop(_dtb_start, node, "#size-cells", &size); in platform_init()
45 fatal("Cannot find #size-cells property"); in platform_init()
48 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type", in platform_init()
68 /* finally, setup the timebase */ in platform_init()
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H A Dtreeboot-currituck.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright 2002-2005 MontaVista Software Inc.
67 if (getprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)) < 0) { in ibm_currituck_fixups()
68 printf("%s: Failed to get dma-ranges\r\n", __func__); in ibm_currituck_fixups()
75 setprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)); in ibm_currituck_fixups()
85 const u32 *timebase; in platform_init() local
92 avail_ram = end_of_ram - (unsigned long)_end; in platform_init()
103 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type", in platform_init()
107 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size); in platform_init()
108 if (timebase && (size == 4)) in platform_init()
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
27 - xlnx,xps-timebase-wdt-1.01.a
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/openbmc/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
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H A Dps3.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #size-cells = <2>;
15 #address-cells = <2>;
33 * dtc expects a clock-frequency and timebase-frequency entries, so
38 * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one
43 #size-cells = <0>;
44 #address-cells = <1>;
49 ibm,ppc-interrupt-server#s = <0x0 0x1>;
50 clock-frequency = <0>;
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/openbmc/u-boot/drivers/cpu/
H A Driscv_cpu.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dm/device-internal.h>
21 return -ENOSPC; in riscv_cpu_get_desc()
32 dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); in riscv_cpu_get_info()
34 mmu = dev_read_string(dev, "mmu-type"); in riscv_cpu_get_info()
36 info->features |= BIT(CPU_FEAT_MMU); in riscv_cpu_get_info()
46 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { in riscv_cpu_get_count()
66 plat->cpu_id = dev_read_addr(dev); in riscv_cpu_bind()
68 ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); in riscv_cpu_bind()
71 dev_read_u32(dev->parent, "timebase-frequency", in riscv_cpu_bind()
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8641si-pre.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
8 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&mpic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
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/openbmc/linux/arch/powerpc/platforms/8xx/
H A Dm8xx_setup.c1 // SPDX-License-Identifier: GPL-2.0
45 /* The cpu node should have timebase and clock frequency properties */ in get_freq()
61 /* The decrementer counts at the system (internal) clock frequency divided by
71 out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, ~KAPWR_KEY); in mpc8xx_calibrate_decr()
72 out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, KAPWR_KEY); in mpc8xx_calibrate_decr()
75 setbits32(&mpc8xx_immr->im_clkrst.car_sccr, 0x02000000); in mpc8xx_calibrate_decr()
77 /* Processor frequency is MHz. in mpc8xx_calibrate_decr()
80 if (!get_freq("clock-frequency", &ppc_proc_freq)) in mpc8xx_calibrate_decr()
81 printk(KERN_ERR "WARNING: Estimating processor frequency " in mpc8xx_calibrate_decr()
85 printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); in mpc8xx_calibrate_decr()
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/openbmc/linux/arch/riscv/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0-only
28 if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) in time_init()
29 panic("RISC-V system with no 'timebase-frequency' in DTS\n"); in time_init()
37 panic("RISC-V ACPI system with no RHCT table\n"); in time_init()
39 riscv_timebase = rhct->time_base_freq; in time_init()
/openbmc/linux/arch/powerpc/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Converted for 64-bit by Mike Corrigan (mikejc@us.ibm.com)
11 * to make clock more stable (2.4.0-test5). The only thing
20 * - improve precision and reproducibility of timebase frequency
22 * - for astronomical applications: add a new function to get
26 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
50 #include <linux/posix-timers.h>
82 .name = "timebase",
155 * or if that doesn't exist return the timebase value passed in.
179 deltascaled = nowscaled - acct->startspurr; in vtime_delta_scaled()
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/openbmc/linux/drivers/pwm/
H A Dpwm-img.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2015, Imagination Technologies
7 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
43 * PWM period is specified with a timebase register,
45 * specified in step periods, in the [0, $timebase] range.
46 * In other words, the timebase imposes the duty cycle
47 * resolution. Therefore, let's constraint the timebase to
49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
83 writel(val, imgchip->base + reg); in img_pwm_writel()
88 return readl(imgchip->base + reg); in img_pwm_readl()
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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/openbmc/u-boot/arch/microblaze/cpu/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
21 return timestamp - base; in get_timer()
22 return timestamp++ - base; in get_timer()
31 while ((get_timer(0) - i) < (usec / 1000)) in __udelay()
40 tmr->control = tmr->control | TIMER_INTERRUPT; in timer_isr()
45 int irq = -1; in timer_init()
48 const void *blob = gd->fdt_blob; in timer_init()
55 if (!(gd->flags & GD_FLG_RELOC)) in timer_init()
59 "xlnx,xps-timer-1.00.a"); in timer_init()
60 if (node != -1) { in timer_init()
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/openbmc/u-boot/arch/arm/cpu/sa1100/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 #include <SA-1100.h>
44 diff = endtime - now; in __udelay()
49 * This function is derived from PowerPC code (read timebase as long long).
58 * This function is derived from PowerPC code (timebase clock frequency).
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dfdt.c1 // SPDX-License-Identifier: GPL-2.0+
17 "timebase-frequency", get_tbclk(), 1); in ft_cpu_setup()
19 "bus-frequency", bd->bi_busfreq, 1); in ft_cpu_setup()
21 "clock-frequency", bd->bi_intfreq, 1); in ft_cpu_setup()
22 do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency", in ft_cpu_setup()
23 bd->bi_intfreq, 1); in ft_cpu_setup()
24 do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", in ft_cpu_setup()
25 gd->arch.brg_clk, 1); in ft_cpu_setup()
27 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); in ft_cpu_setup()
/openbmc/u-boot/arch/m68k/lib/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0+
43 usec = usec - tmp; in __udelay()
45 /* Set up TIMER 3 as timebase clock */ in __udelay()
46 timerp->tmr = DTIM_DTMR_RST_RST; in __udelay()
47 timerp->tcn = 0; in __udelay()
49 timerp->tmr = in __udelay()
53 start = now = timerp->tcn; in __udelay()
55 now = timerp->tcn; in __udelay()
65 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); in dtimer_interrupt()
83 timerp->tcn = 0; in timer_init()
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dfdt.c1 // SPDX-License-Identifier: GPL-2.0
22 "timebase-frequency", bd->bi_busfreq / 4, 1); in ft_cpu_setup()
24 "bus-frequency", bd->bi_busfreq, 1); in ft_cpu_setup()
26 "clock-frequency", bd->bi_intfreq, 1); in ft_cpu_setup()
28 "bus-frequency", bd->bi_busfreq, 1); in ft_cpu_setup()
30 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); in ft_cpu_setup()
34 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); in ft_cpu_setup()
/openbmc/linux/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
120 " - USERSPACE CAN LOCK THIS KERNEL!\n", __func__); in setup_cpuinfo()
132 /* take timebase-frequency from DTS */ in setup_cpuinfo_clk()
133 cpuinfo.cpu_clock_freq = fcpu(cpu, "timebase-frequency"); in setup_cpuinfo_clk()
139 pr_err("ERROR: CPU clock frequency not setup\n"); in setup_cpuinfo_clk()
/openbmc/u-boot/arch/arm/cpu/arm920t/imx/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
18 #include <asm/arch/imx-regs.h>
46 return get_timer_masked() - base; in get_timer()
56 diff = endtime - now; in __udelay()
61 * This function is derived from PowerPC code (read timebase as long long).
70 * This function is derived from PowerPC code (timebase clock frequency).
83 /* Disable watchdog and set Time-Out field to 0 */ in reset_cpu()
/openbmc/linux/arch/powerpc/kvm/
H A Demulate.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <asm/ppc-opcode.h>
31 pr_debug("mtDEC: %lx\n", vcpu->arch.dec); in kvmppc_emulate_dec()
32 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); in kvmppc_emulate_dec()
41 if (vcpu->arch.dec == 0) in kvmppc_emulate_dec()
46 * The decrementer ticks at the same rate as the timebase, so in kvmppc_emulate_dec()
51 dec_time = vcpu->arch.dec; in kvmppc_emulate_dec()
53 * Guest timebase ticks at the same frequency as host timebase. in kvmppc_emulate_dec()
54 * So use the host timebase calculations for decrementer emulation. in kvmppc_emulate_dec()
58 hrtimer_start(&vcpu->arch.dec_timer, in kvmppc_emulate_dec()
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/openbmc/u-boot/arch/arm/cpu/armv7/stv0991/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
9 #include <asm/arch-stv0991/hardware.h>
10 #include <asm/arch-stv0991/stv0991_cgu.h>
11 #include <asm/arch-stv0991/stv0991_gpt.h>
16 #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
21 #define timestamp gd->arch.tbl
22 #define lastdec gd->arch.lastinc
29 writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq); in timer_init()
30 writel(readl(&stv0991_cgu_regs->cgu_enable_2) | in timer_init()
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/openbmc/u-boot/arch/arm/mach-omap2/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Richard Woodruff <r-woodruff2@ti.com>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
39 writel(TIMER_LOAD_VAL, &timer_base->tldr); in timer_init()
42 &timer_base->tclr); in timer_init()
52 return get_timer_masked() - base; in get_timer()
59 unsigned long now, last = readl(&timer_base->tcrr); in __udelay()
62 now = readl(&timer_base->tcrr); in __udelay()
64 tmo -= TIMER_OVERFLOW_VAL - last + now + 1; in __udelay()
66 tmo -= now - last; in __udelay()
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