1 // SPDX-License-Identifier: GPL-2.0
45 	/* The cpu node should have timebase and clock frequency properties */  in get_freq()
61 /* The decrementer counts at the system (internal) clock frequency divided by
71 	out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, ~KAPWR_KEY);  in mpc8xx_calibrate_decr()
72 	out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, KAPWR_KEY);  in mpc8xx_calibrate_decr()
75 	setbits32(&mpc8xx_immr->im_clkrst.car_sccr, 0x02000000);  in mpc8xx_calibrate_decr()
77 	/* Processor frequency is MHz.  in mpc8xx_calibrate_decr()
80 	if (!get_freq("clock-frequency", &ppc_proc_freq))  in mpc8xx_calibrate_decr()
81 		printk(KERN_ERR "WARNING: Estimating processor frequency "  in mpc8xx_calibrate_decr()
85 	printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);  in mpc8xx_calibrate_decr()
87 	/* Perform some more timer/timebase initialization.  This used  in mpc8xx_calibrate_decr()
102 	out_be32(&mpc8xx_immr->im_sitk.sitk_tbscrk, ~KAPWR_KEY);  in mpc8xx_calibrate_decr()
103 	out_be32(&mpc8xx_immr->im_sitk.sitk_rtcsck, ~KAPWR_KEY);  in mpc8xx_calibrate_decr()
104 	out_be32(&mpc8xx_immr->im_sitk.sitk_tbk, ~KAPWR_KEY);  in mpc8xx_calibrate_decr()
105 	out_be32(&mpc8xx_immr->im_sitk.sitk_tbscrk, KAPWR_KEY);  in mpc8xx_calibrate_decr()
106 	out_be32(&mpc8xx_immr->im_sitk.sitk_rtcsck, KAPWR_KEY);  in mpc8xx_calibrate_decr()
107 	out_be32(&mpc8xx_immr->im_sitk.sitk_tbk, KAPWR_KEY);  in mpc8xx_calibrate_decr()
110 	clrbits16(&mpc8xx_immr->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));  in mpc8xx_calibrate_decr()
113 	setbits16(&mpc8xx_immr->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));  in mpc8xx_calibrate_decr()
115 	/* Enabling the decrementer also enables the timebase interrupts  in mpc8xx_calibrate_decr()
117 	 * we have to enable the timebase).  The decrementer interrupt  in mpc8xx_calibrate_decr()
125 	out_be16(&mpc8xx_immr->im_sit.sit_tbscr,  in mpc8xx_calibrate_decr()
126 		 ((1 << (7 - (irq / 2))) << 8) | (TBSCR_TBF | TBSCR_TBE));  in mpc8xx_calibrate_decr()
135  * modify, and re-lock.
144 	out_be32(&mpc8xx_immr->im_sitk.sitk_rtck, KAPWR_KEY);  in mpc8xx_set_rtc_time()
145 	out_be32(&mpc8xx_immr->im_sit.sit_rtc, (u32)time);  in mpc8xx_set_rtc_time()
146 	out_be32(&mpc8xx_immr->im_sitk.sitk_rtck, ~KAPWR_KEY);  in mpc8xx_set_rtc_time()
156 	data = in_be32(&mpc8xx_immr->im_sit.sit_rtc);  in mpc8xx_get_rtc_time()
165 	setbits32(&mpc8xx_immr->im_clkrst.car_plprcr, 0x00000080);  in mpc8xx_restart()
170 	in_8(&mpc8xx_immr->im_clkrst.res[0]);  in mpc8xx_restart()