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/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb-11mp.dts23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile";
31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
38 #address-cells = <1>;
39 #size-cells = <0>;
40 enable-method = "arm,realview-smp";
46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
[all …]
H A Darm-realview-eb-mp.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
[all …]
H A Darm-realview-eb.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "arm-realview-eb.dtsi"
30 compatible = "arm,realview-eb";
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
[all …]
H A Darm-realview-eb-a9mp.dts23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
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/openbmc/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dcache.json3 …the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might in…
17 "BriefDescription": "Counts the number of L2 cache misses",
24 "BriefDescription": "Counts the total number of L2 cache references.",
31cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions …
37 "BriefDescription": "Counts all the load micro-ops retired",
40 "PublicDescription": "This event counts the number of load micro-ops retired.",
45 "BriefDescription": "Counts all the store micro-ops retired",
48 "PublicDescription": "This event counts the number of store micro-ops retired.",
53 …ion": "Counts the loads retired that get the data from the other core in the same tile in M state",
62 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache",
[all …]
/openbmc/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h38 * further describe the buffer's format - for example tiling or compression.
41 * ----------------
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * may preserve meaning - such as number of planes - from the fourcc code,
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75 * - Kernel and user-space drivers: for drivers it's important that modifiers
79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92 * -----------------------
97 * upstream in-kernel or open source userspace user does not apply.
221 * IEEE 754-2008 binary16 half-precision float
[all …]
/openbmc/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
222 * IEEE 754-2008 binary16 half-precision float
[all …]
H A Dv3d_drm.h2 * Copyright © 2014-2018 Broadcom
63 /* struct drm_v3d_extension - ioctl extensions
65 * Linked-list of generic extensions where the id identify which struct is
76 /* struct drm_v3d_sem - wait/signal semaphore
99 * struct drm_v3d_multi_sync - ioctl extension to add support multiples
124 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
131 * each CL executes. The VCD cache should be flushed (if necessary)
143 * then writes out the state updates and draw calls necessary per tile
144 * to the tile allocation BO.
148 * clients -- that is left up to the submitter to control
[all …]
H A Dmsm_drm.h35 * subject to backwards-compatibility constraints:
52 /* The pipe-id just uses the lower bits, so can be OR'd with flags in
54 * we extend/overload the pipe-id some day to deal with multiple rings,
61 /* timeouts are specified in clock-monotonic absolute times (to simplify
70 /* Below "RO" indicates a read-only param, "WO" indicates write-only, and
85 #define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */
102 __u32 len; /* zero for non-pointer params */
113 /* cache modes */
145 __u32 info; /* in - one of MSM_INFO_* */
178 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
[all …]
H A Detnaviv_drm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
28 * subject to backwards-compatibility constraints:
40 /* timeouts are specified in clock-monotonic absolute times (to simplify
94 /* cache modes */
133 * relocbuf->gpuaddr + reloc_offset
147 * one) entry in the submit->bos[] table.
184 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
236 __u32 handle; /* out, non-zero handle */
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
16 architecture. With configurable address mapping look up tables and per tile
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
[all …]
/openbmc/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_issues.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
16 /* Need way to guarantee that all previously-translated memory accesses
20 /* On job complete with non-done the cache is not flushed */
31 * same time as access to a valid page in the same uTLB cache line ( ==
43 /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
44 * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
53 /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
57 /* HT: Tiler returns TERMINATED for non-terminated command */
71 /* Missing cache flush in multi core-group configuration */
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c1 // SPDX-License-Identifier: MIT
16 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
21 * the cache-line pairs. The compression state of the cache-line pair
22 * is specified by 2 bits in the CCS. Each CCS cache-line represents
23 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
24 * cache-line-pairs. CCS is always Y tiled."
26 * Since cache line pairs refers to horizontally adjacent cache lines,
27 * each cache line in the CCS corresponds to an area of 32x16 cache
44 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
45 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c30 #include <linux/dma-mapping.h>
52 * NV10-NV40 tiling helpers
60 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
61 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); in nv10_bo_update_tile_region()
62 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
64 nouveau_fence_unref(&reg->fence); in nv10_bo_update_tile_region()
66 if (tile->pitch) in nv10_bo_update_tile_region()
67 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
72 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dgbefb.c4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
102 .height = -1,
103 .width = -1,
133 .height = -1,
134 .width = -1,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c889 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
890 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
891 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
892 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
901 * gfx_v7_0_init_microcode - load ucode images from disk
917 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
938 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v7_0_init_microcode()
943 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v7_0_init_microcode()
[all …]
/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_drv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 #include <kunit/test-bug.h>
95 /* The kernel-space BO cache. Tracks buffers that have been
100 /* Array of list heads for entries in the BO cache,
102 * in the cache when allocating.
107 /* List of all BOs in the cache, ordered by age, so we
185 /* The memory used for storing binner tile alloc, tile state,
254 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
258 /* Time in jiffies when the BO was put in vc4->bo_cache. */
261 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dcik.c144 * cik_get_allowed_info_register - fetch the register for the info ioctl
150 * Returns 0 for success or -EINVAL for an invalid register
172 return -EINVAL; in cik_get_allowed_info_register()
184 spin_lock_irqsave(&rdev->didt_idx_lock, flags); in cik_didt_rreg()
187 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); in cik_didt_rreg()
195 spin_lock_irqsave(&rdev->didt_idx_lock, flags); in cik_didt_wreg()
198 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); in cik_didt_wreg()
227 actual_temp = (temp / 8) - 49; in kv_get_temp()
242 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in cik_pciep_rreg()
246 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in cik_pciep_rreg()
[all …]
H A Dsi.c1230 switch (rdev->family) { in si_init_golden_registers()
1298 * si_get_allowed_info_register - fetch the register for the info ioctl
1304 * Returns 0 for success or -EINVAL for an invalid register
1323 return -EINVAL; in si_get_allowed_info_register()
1331 * si_get_xclk - get the xclk
1340 u32 reference_clock = rdev->clock.spll.reference_freq; in si_get_xclk()
1580 if (!rdev->mc_fw) in si_mc_load_microcode()
1581 return -EINVAL; in si_mc_load_microcode()
1583 if (rdev->new_fw) { in si_mc_load_microcode()
1585 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data; in si_mc_load_microcode()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
/openbmc/linux/drivers/gpu/drm/v3d/
H A Dv3d_drv.h1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
130 * jobs, to keep the sched-fence seqnos in order.
134 /* Lock taken during a cache clean and when initiating an L2
155 return v3d->ver >= 41; in v3d_has_csd()
158 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
160 /* The per-fd struct, which tracks the MMU mappings. */
178 * v3d_render_job->unref_list
203 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
204 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
[all …]
/openbmc/linux/drivers/gpu/drm/
H A Ddrm_connector.c51 * Hence they are reference-counted using drm_connector_get() and
67 * For connectors which are not fixed (like built-in panels) the driver needs to
76 * Note drm_connector_[un]register() first take connector->lock and then
94 { DRM_MODE_CONNECTOR_DVII, "DVI-I" },
95 { DRM_MODE_CONNECTOR_DVID, "DVI-D" },
96 { DRM_MODE_CONNECTOR_DVIA, "DVI-A" },
103 { DRM_MODE_CONNECTOR_HDMIA, "HDMI-A" },
104 { DRM_MODE_CONNECTOR_HDMIB, "HDMI-B" },
132 * drm_get_connector_type_name - return a string for connector type
147 * drm_connector_get_cmdline_mode - reads the user's cmdline mode
[all …]
/openbmc/linux/arch/x86/kernel/fpu/
H A Dxstate.c1 // SPDX-License-Identifier: GPL-2.0-only
47 "AVX-512 opmask",
48 "AVX-512 Hi256",
49 "AVX-512 ZMM_Hi256",
53 "Control-flow User registers",
54 "Control-flow Kernel registers (unused)",
59 "AMX Tile config",
60 "AMX Tile data",
82 { [ 0 ... XFEATURE_MAX - 1] = -1};
84 { [ 0 ... XFEATURE_MAX - 1] = -1};
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_domain.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2014-2016 Intel Corporation
21 #define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
25 struct drm_i915_private *i915 = to_i915(obj->base.dev); in gpu_write_needs_clflush()
35 * whether the object is un-cached or write-through. in gpu_write_needs_clflush()
43 struct drm_i915_private *i915 = to_i915(obj->base.dev); in i915_gem_cpu_write_needs_clflush()
45 if (obj->cache_dirty) in i915_gem_cpu_write_needs_clflush()
51 if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) in i915_gem_cpu_write_needs_clflush()
65 if (!(obj->write_domain & flush_domains)) in flush_write_domain()
68 switch (obj->write_domain) { in flush_write_domain()
[all …]
/openbmc/linux/include/asm-generic/
H A Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
32 * Generic MMU-gather implementation.
49 * - tlb_gather_mmu() / tlb_gather_mmu_fullmm() / tlb_finish_mmu()
56 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
61 * - tlb_remove_table()
63 * tlb_remove_table() is the basic primitive to free page-table directories
70 * - tlb_remove_page() / __tlb_remove_page()
71 * - tlb_remove_page_size() / __tlb_remove_page_size()
81 * - tlb_change_page_size()
[all …]

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