Lines Matching +full:tile +full:- +full:cache
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
130 * jobs, to keep the sched-fence seqnos in order.
134 /* Lock taken during a cache clean and when initiating an L2
155 return v3d->ver >= 41; in v3d_has_csd()
158 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
160 /* The per-fd struct, which tracks the MMU mappings. */
178 * v3d_render_job->unref_list
203 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
204 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
206 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
207 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
209 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
210 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
212 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
213 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
256 /* Submitted tile memory allocation start/size, tile state. */
304 * __wait_for - magic wait macro
326 ret__ = -ETIMEDOUT; \