Lines Matching +full:tile +full:- +full:cache
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
222 * IEEE 754-2008 binary16 half-precision float
232 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
248 …010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only …
252 * 16-xx padding occupy lsb
260 * 16-xx padding occupy lsb except Y410
272 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
285 * 1-plane YUV 4:2:0
288 * These formats can only be used with a non-Linear modifier.
318 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
319 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
362 /* 3 plane non-subsampled (444) YCbCr
370 /* 3 plane non-subsampled (444) YCrCb
395 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
396 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
402 * Format modifiers describe, typically, a re-ordering or modification
406 * The upper 8 bits of the format modifier are a vendor-id as assigned
425 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
445 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
447 * compatibility, in cases where a vendor-specific definition already exists and
452 * generic layouts (such as pixel re-ordering), which may have
453 * independently-developed support across multiple vendors.
456 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
483 * which tells the driver to also take driver-internal information into account
493 * used is out-of-band information carried in an API-specific way (e.g. in a
501 * Intel X-tiling layout
504 * in row-major layout. Within the tile bytes are laid out row-major, with
505 * a platform-dependent stride. On top of that the memory can apply
506 * platform-depending swizzling of some higher address bits into bit6.
510 * cross-driver sharing. It exists since on a given platform it does uniquely
511 * identify the layout in a simple way for i915-specific userspace, which
518 * Intel Y-tiling layout
521 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
522 * chunks column-major, with a platform-dependent height. On top of that the
523 * memory can apply platform-depending swizzling of some higher address bits
528 * cross-driver sharing. It exists since on a given platform it does uniquely
529 * identify the layout in a simple way for i915-specific userspace, which
536 * Intel Yf-tiling layout
538 * This is a tiled layout using 4Kb tiles in row-major layout.
539 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
540 * are arranged in four groups (two wide, two high) with column-major layout.
542 * out as 2x2 column-major.
554 * The main surface will be plane index 0 and must be Y/Yf-tiled,
557 * Each CCS tile matches a 1024x512 pixel area of the main surface.
562 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
571 * Intel color control surfaces (CCS) for Gen-12 render compression.
573 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
574 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
575 * main surface. In other words, 4 bits in CCS map to a main surface cache
577 * Y-tile widths.
582 * Intel color control surfaces (CCS) for Gen-12 media compression
584 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
585 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
586 * main surface. In other words, 4 bits in CCS map to a main surface cache
588 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
595 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
598 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
607 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
609 * pitch is required to be a multiple of 4 tile widths.
614 * Intel Tile 4 layout
616 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
617 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
618 * only differs from Tile Y at the 256B granularity in between. At this
619 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
627 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
630 * main surface pitch is required to be a multiple of four Tile 4 widths.
637 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
638 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
642 * pitch is required to be a multiple of four Tile 4 widths.
649 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
652 * main surface pitch is required to be a multiple of four Tile 4 widths. The
664 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
665 * main surface. In other words, 4 bits in CCS map to a main surface cache
675 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
676 * main surface. In other words, 4 bits in CCS map to a main surface cache
678 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
697 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
699 * pitch is required to be a multiple of 4 tile widths.
704 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
706 * Macroblocks are laid in a Z-shape, and each pixel data is following the
711 * - multiple of 128 pixels for the width
712 * - multiple of 32 pixels for the height
714 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
719 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
721 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
731 * Implementation may be platform and base-format specific.
744 * Implementation may be platform and base-format specific.
757 * Implementation may be platform and base-format specific.
767 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
773 * Vivante 64x64 super-tiling layout
775 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
776 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
780 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
785 * Vivante 4x4 tiling layout for dual-pipe
787 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
789 * compared to the non-split tiled layout.
794 * Vivante 64x64 super-tiling layout for dual-pipe
796 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
798 * therefore halved compared to the non-split super-tiled layout.
803 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
805 * separate buffer containing the clear/compression status of each tile. The
807 * tile size in bytes covered by one entry in the status buffer and s is the
809 * We reserve the top 8 bits of the Vivante modifier space for tile status
855 * ---- ----- -----------------------------------------------------------------
859 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
861 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
863 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
865 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
873 * 11:9 - Reserved (To support 2D-array textures with variable array stride
874 * in blocks, specified via log2(tile width in blocks)). Must be
894 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
895 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
905 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
921 * 55:25 - Reserved for future use. Must be zero.
933 * with block-linear layouts, is remapped within drivers to the value 0xfe,
934 * which corresponds to the "generic" kind used for simple single-sample
935 * uncompressed color formats on Fermi - Volta GPUs.
952 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
995 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
997 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1006 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1009 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1012 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1013 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
1016 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1017 * tiles) or right-to-left (odd rows of 4k tiles).
1040 * and UV. Some SAND-using hardware stores UV in a separate tiled
1084 * the assumption is that a no-XOR tiling modifier will be created.
1092 * It provides fine-grained random access and minimizes the amount of data
1097 * and different devices or use-cases may support different combinations.
1129 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1146 * AFBC block-split
1167 * AFBC copy-block restrict
1169 * Buffers with this flag must obey the copy-block restriction. The restriction
1170 * is such that there are no copy-blocks referring across the border of 8x8
1179 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1183 * to the tile size.
1190 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1196 * AFBC double-buffer
1198 * Indicates that the buffer is allocated in a layout safe for front-buffer
1206 * Indicates that the buffer includes per-superblock content hints.
1223 * Arm Fixed-Rate Compression (AFRC) modifiers
1227 * reductions in graphics and media use-cases.
1243 * ---------------- ---------------
1249 * to a multiple of the paging tile dimensions.
1250 * The dimensions of each paging tile depend on whether the buffer is optimised for
1253 * Layout Paging Tile Width Paging Tile Height
1254 * ------ ----------------- ------------------
1263 * ----------------------------- --------- ----------------- ------------------
1266 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1267 * ----------------------------- --------- ----------------- ------------------
1270 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1271 * ----------------------------- --------- ----------------- ------------------
1273 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1274 * ----------------------------- --------- ----------------- ------------------
1277 * ----------------------------- --------- ----------------- ------------------
1296 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1301 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1303 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1305 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1319 * Indicates if the buffer uses the scanline-optimised layout
1320 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1326 * Arm 16x16 Block U-Interleaved modifier
1344 * The pixel order in each tile is linear and the tiles are disposed linearly,
1345 * both in row-major order.
1359 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1361 * - DRM_FORMAT_YUV420_8BIT
1362 * - DRM_FORMAT_YUV420_10BIT
1386 * - a body content organized in 64x32 superblocks with 4096 bytes per
1388 * - a 32 bytes per 128x64 header block
1406 * be accessible by the user-space clients, but only accessible by the
1409 * The user-space clients should expect a failure while trying to mmap
1410 * the DMA-BUF handle returned by the producer.
1435 * - main surface
1438 * - main surface in plane 0
1439 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1442 * - main surface in plane 0
1443 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1444 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1446 * For multi-plane formats the above surfaces get merged into one plane for
1450 * ----- ------------------------ ---------------------------------------------
1453 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1466 * 55:36 - Reserved for future use, must be zero
1486 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1498 * 0 - LINEAR
1499 * 1 - 256B_2D - 2D block dimensions
1500 * 2 - 4KB_2D
1501 * 3 - 64KB_2D
1502 * 4 - 256KB_2D
1503 * 5 - 4KB_3D - 3D block dimensions
1504 * 6 - 64KB_3D
1505 * 7 - 256KB_3D
1527 * one which is not-aligned.
1557 * relevant for GFX9 and later and if the tile field is *_X/_T.