Searched +full:stm32 +full:- +full:uart (Results 1 – 14 of 14) sorted by relevance
2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved3 * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.5 * This file is dual-licensed: you can use it either under the terms45 #include "armv7-m.dtsi"46 #include <dt-bindings/clock/stm32fx-clock.h>47 #include <dt-bindings/mfd/stm32f4-rcc.h>51 clk_hse: clk-hse {52 #clock-cells = <0>;53 compatible = "fixed-clock";54 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/clock/stm32mp1-clks.h>8 #include <dt-bindings/reset/stm32mp1-resets.h>11 #address-cells = <1>;12 #size-cells = <1>;15 #address-cells = <1>;16 #size-cells = <0>;19 compatible = "arm,cortex-a7";[all …]
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>4 * This file is dual-licensed: you can use it either under the terms44 #include "armv7-m.dtsi"45 #include <dt-bindings/clock/stm32h7-clks.h>46 #include <dt-bindings/mfd/stm32h7-rcc.h>50 clk_hse: clk-hse {51 #clock-cells = <0>;52 compatible = "fixed-clock";53 clock-frequency = <25000000>;56 clk_lse: clk-lse {[all …]
2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>9 * This file is dual-licensed: you can use it either under the terms48 #include "armv7-m.dtsi"49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>50 #include <dt-bindings/clock/stm32fx-clock.h>51 #include <dt-bindings/mfd/stm32f7-rcc.h>55 clk_hse: clk-hse {56 #clock-cells = <0>;[all …]
1 SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause3 # Copyright (C) 2018 STMicroelectronics - All Rights Reserved6 U-Boot on STMicroelectronics STM32MP115 U-Boot supports one STMP32MP1 SoCs: STM32MP15717 The STM32MP157 is a Cortex-A MPU aimed at various applications.19 - Dual core Cortex-A7 application core20 - 2D/3D image composition with GPU21 - Standard memories interface support22 - Standard connectivity, widely inherited from the STM32 MCU family23 - Comprehensive security support[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved14 #include <asm/arch/stm32.h>22 bool stm32f4 = uart_info->stm32f4; in _stm32_serial_setbrg()45 _stm32_serial_setbrg(plat->base, plat->uart_info, in stm32_serial_setbrg()46 plat->clock_rate, baudrate); in stm32_serial_setbrg()54 bool stm32f4 = plat->uart_info->stm32f4; in stm32_serial_setconfig()55 u8 uart_enable_bit = plat->uart_info->uart_enable_bit; in stm32_serial_setconfig()56 u32 cr1 = plat->base + CR1_OFFSET(stm32f4); in stm32_serial_setconfig()68 return -ENOTSUPP; /* not supported in driver*/ in stm32_serial_setconfig()[all …]
11 Select a default baudrate, where "default" has a driver-specific12 meaning of either setting the baudrate for the early debug UART19 # non-dm serial code32 In various cases, we need to specify which of the UART devices that34 in U-Boot.41 In very space-constrained devices even the full UART driver is too42 large. In this case the debug UART can still be used in some cases.43 This option enables the full UART in U-Boot, so if is it disabled,44 the full UART driver will be omitted, thus saving space.51 In very space-constrained devices even the full UART driver is too[all …]
7 bool "Theobroma Systems RK3368-uQ7 (Lion) module"9 The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,10 MXM-230 connector) system-on-module designed by Theobroma14 - 8x Cortex-A53 (in 2 clusters of 4 cores each)15 - (on-module) up to 4GB of DDR3 memory16 - (on-module) SPI-NOR flash17 - (on-module) eMMC18 - Gigabit Ethernet (with an on-module KSZ9031 PHY)19 - USB20 - HDMI[all …]
50 bool "Rockchip e-fuse support"53 Enable (read-only) access for the e-fuse block found in Rockchip55 or through child-nodes that are generated based on the e-fuse map74 Enable command-line access to the Chrome OS EC (Embedded76 a number of sub-commands for performing EC tasks such as112 keyboard (use the -l flag to enable the LCD), verified boot context,121 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface129 integrated 64-byte EEPROM, four programmable non-volatile I/O pins159 disable the legacy UART, the watchdog or other devices163 bool "Enable power-sequencing drivers"[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved11 #include <asm/arch/stm32.h>48 * - boot instance = bit 31:1649 * - boot device = bit 15:0125 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ in dbgmcu_init()178 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; in arch_cpu_init()190 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()249 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; in setup_boot_mode()257 env_set("boot_device", "uart"); in setup_boot_mode()[all …]
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10 consult qemu-devel and not any specific individual privately.23 W: Web-page with status/info59 ------------------------------63 L: qemu-devel@nongnu.org72 R: Philippe Mathieu-Daudé <philmd@linaro.org>75 F: docs/devel/build-environment.rst76 F: docs/devel/code-of-conduct.rst78 F: docs/devel/conflict-resolution.rst80 F: docs/devel/submitting-a-patch.rst81 F: docs/devel/submitting-a-pull-request.rst[all …]
1 2025-12-15 03:01:05.452-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-15 03:01:05.518-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]
1 2025-12-14 03:01:07.427-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-14 03:01:07.482-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]