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/openbmc/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pm.c1 // SPDX-License-Identifier: GPL-2.0
12 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs,
24 static void __iomem *sram; variable
44 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
46 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); in mpc52xx_set_wakeup_gpio()
48 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
50 tmp = in_be16(&gpiow->wkup_itype); in mpc52xx_set_wakeup_gpio()
53 out_be16(&gpiow->wkup_itype, tmp); in mpc52xx_set_wakeup_gpio()
55 out_8(&gpiow->wkup_maste, 1); in mpc52xx_set_wakeup_gpio()
64 { .compatible = "fsl,mpc5200-immr", }, in mpc52xx_pm_prepare()
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/openbmc/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
99 functions of the driver includes re-configuring AC timing
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/openbmc/linux/arch/arm/mach-rockchip/
H A Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
24 /* olny cpu0 can continue to run, the others is halt here */
64 .word . - rockchip_slp_cpu_resume
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dmediatek,mt6357-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/mediatek,mt6357-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen Zhong <chen.zhong@mediatek.com>
11 - Fabien Parent <fabien.parent@linaro.org>
12 - Alexandre Mergnat <amergnat@baylibre.com>
17 - buck-<name>
18 - ldo-<name>.
22 "^buck-v(core|modem|pa|proc|s1)$":
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/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
18 format into FPGA's SRAM configuration memory.
23 - lattice,sysconfig-ecp5
28 program-gpios:
34 init-gpios:
40 done-gpios:
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/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dconfig.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Written-by: Lei Wen <leiwen@marvell.com>
31 * EHCI driver (ehci-marvell.c) and possibly others rely on the data
45 /* Kirkwood has 2k of Security SRAM, use it for SP */
87 /* Needs byte-swapping for ATA data register */
93 /* Each 8-bit ATA register is aligned to a 4-bytes address */
95 /* Controller supports 48-bits LBA addressing */
/openbmc/linux/drivers/net/wireless/intel/iwlegacy/
H A Dprph.h8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
105 * in special SRAM that does not power down when the embedded control
106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
109 * internally loads the short bootstrap program from the special SRAM into the
110 * embedded processor's instruction SRAM, and starts the processor so it runs
119 * The uCode used for open-source drivers includes two programs:
121 * 1) Initialization -- performs hardware calibration and sets up some
128 * 2) Runtime/Protocol -- performs all normal runtime operations. This
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/openbmc/qemu/docs/system/arm/
H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
6 servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an
11 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
13 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
16 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
18 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
21 - ``quanta-gbs-bmc`` Quanta GBS server BMC
22 - ``quanta-gsj`` Quanta GSJ server BMC
23 - ``kudo-bmc`` Fii USA Kudo server BMC
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/openbmc/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_virt_prcm_set.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
38 #include "cm-regbits-24xx.h"
40 #include "sram.h"
48 * sys_ck_rate: the rate of the external high-frequency clock
49 * oscillator on the board. Set by the SoC-specific clock init code.
55 * omap2_table_mpu_recalc - just return the MPU speed
63 return curr_prcm_set->mpu_speed; in omap2_table_mpu_recalc()
[all …]
H A Dsdrc2xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Richard Woodruff <r-woodruff2@ti.com>
28 #include "sram.h"
120 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. in omap2xxx_sdrc_init_params()
151 /* No disruptions, DDR will be offline & C-ABI not followed */ in omap2xxx_sdrc_init_params()
/openbmc/linux/drivers/remoteproc/
H A Dti_k3_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
9 #include <linux/dma-mapping.h>
19 #include <linux/omap-mailbox.h>
33 /* R5 TI-SCI Processor Configuration Flags */
47 /* R5 TI-SCI Processor Control Flags */
50 /* R5 TI-SCI Processor Status Flags */
59 * struct k3_r5_mem - internal memory structure
77 * Single-CPU mode : AM64x SoCs only
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/openbmc/linux/drivers/mtd/nand/raw/
H A Dvf610_nfc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
15 * - Untested on MPC5125 and M54418.
16 * - DMA and pipelining not used.
17 * - 2K pages or less.
18 * - HW ECC: Only 2K page with 64+ OOB.
19 * - HW ECC: Only 24 and 32-bit error correction implemented.
66 #define COMMAND_NADDR_BYTES(x) GENMASK(13, 13 - (x) + 1)
135 * ECC status - seems to consume 8 bytes (double word). The documented
140 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
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/openbmc/u-boot/tools/binman/
H A DREADME.entries9 Note that some entries are subclasses of others, using and extending their
15 ------------------------------------------------------
21 - filename: Filename of file to read into entry
22 - compress: Compression algorithm to use:
24 lz4: Use lz4 compression (via 'lz4' command-line utility)
28 example the 'u_boot' entry which provides the filename 'u-boot.bin'.
30 If compression is enabled, an extra 'uncomp-size' property is written to
31 the node (if enabled with -u) which provides the uncompressed size of the
36 Entry: blob-dtb: A blob that holds a device tree
37 ------------------------------------------------
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/openbmc/qemu/hw/arm/
H A Dallwinner-r40.c22 #include "qemu/error-report.h"
27 #include "hw/qdev-core.h"
29 #include "hw/char/serial-mm.h"
31 #include "hw/usb/hcd-ehci.h"
34 #include "hw/arm/allwinner-r40.h"
35 #include "hw/misc/allwinner-r40-dramc.h"
36 #include "target/arm/cpu-qom.h"
87 { "d-engine", 0x01000000, 4 * MiB },
88 { "d-inter", 0x01400000, 128 * KiB },
96 { "usb0-otg", 0x01c13000, 4 * KiB },
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/openbmc/linux/drivers/net/wireless/intersil/hostap/
H A Dhostap_download.c1 // SPDX-License-Identifier: GPL-2.0
11 local = iface->local; in prism2_enable_aux_port()
13 if (local->no_pri) { in prism2_enable_aux_port()
15 PDEBUG(DEBUG_EXTRA2, "%s: no PRI f/w - assuming Aux " in prism2_enable_aux_port()
16 "port is already enabled\n", dev->name); in prism2_enable_aux_port()
21 spin_lock_irqsave(&local->cmdlock, flags); in prism2_enable_aux_port()
26 tries--; in prism2_enable_aux_port()
31 spin_unlock_irqrestore(&local->cmdlock, flags); in prism2_enable_aux_port()
32 printk("%s: prism2_enable_aux_port - timeout - reg=0x%04x\n", in prism2_enable_aux_port()
33 dev->name, reg); in prism2_enable_aux_port()
[all …]
/openbmc/linux/drivers/misc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 See Documentation/misc-devices/ad525x_dpot.rst for the
40 module will be called ad525x_dpot-i2c.
51 module will be called ad525x_dpot-spi.
65 This option enables device driver support for in-band access to the
78 website <https://www-03.ibm.com/systems/info/x86servers/serverproven/compat/us/>
175 hardware based memory protection from the others. Enabling
189 called smpro-errmon.
199 called smpro-misc.
202 tristate "CS5535/CS5536 Geode Multi-Function General Purpose Timer (MFGPT) support"
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/openbmc/linux/drivers/atm/
H A Didt77252.h44 (((vpi) << card->vcibits) | ((vci) & card->vcimask))
107 #define SAR_FB_SIZE_0 (2048 - 256)
108 #define SAR_FB_SIZE_1 (4096 - 256)
109 #define SAR_FB_SIZE_2 (8192 - 256)
110 #define SAR_FB_SIZE_3 (16384 - 256)
158 #define SCQ_MASK (SCQ_SIZE - 1)
228 /* RCTE - Receive Connection Table Entry */
242 /* RSQ - Receive Status Queue */
280 /* TSQ - Transmit Status Queue */
335 #define FBQ_MASK (FBQ_SIZE - 1)
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/openbmc/linux/drivers/soc/qcom/
H A Docmem.c1 // SPDX-License-Identifier: GPL-2.0-only
103 writel(data, ocmem->mmio + reg); in ocmem_write()
108 return readl(ocmem->mmio + reg); in ocmem_read()
117 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
118 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
120 if (region->mode == THIN_MODE) in update_ocmem()
124 dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n", in update_ocmem()
129 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
130 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
133 data = OCMEM_PSGSC_CTL_MACRO0_MODE(region->macro_state[0]) | in update_ocmem()
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/openbmc/linux/drivers/edac/
H A DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
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/openbmc/linux/drivers/net/fddi/
H A Ddefza.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
45 * unsupported partial-word accesses
93 #define FZA_HALT_HOST 0x01 /* host-directed HALT */
95 #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
102 #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
104 #define FZA_TEST_SRAM_BWADDR 0x02 /* SRAM byte/word address */
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A Dinternal.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2003-2015, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-fh.h"
19 #include "iwl-csr.h"
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
22 #include "iwl-io.h"
23 #include "iwl-op-mode.h"
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dvf610_nfc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
6 * Ported to U-Boot by Stefan Agner
17 * - Untested on MPC5125 and M54418.
18 * - DMA and pipelining not used.
19 * - 2K pages or less.
20 * - HW ECC: Only 2K page with 64+ OOB.
21 * - HW ECC: Only 24 and 32-bit error correction implemented.
62 * - 31.4.7 Flash Command Code Description, Vybrid manual
63 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
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/openbmc/linux/drivers/net/ethernet/amd/
H A Dpcnet32.c3 * Copyright 1996-1999 Thomas Bogendoerfer
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
127 /* 14 MII 100BaseTx-FD */
175 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
177 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
228 /* The PCNET32 32-Bit initialization block, described in databook. */
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
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/openbmc/linux/Documentation/arch/sh/
H A Dnew-machine.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Paul Mundt <lethal@linux-sh.org>
18 of the board-specific code (with the exception of stboards) ended up
19 in arch/sh/kernel/ directly, with board-specific headers ending up in
20 include/asm-sh/. For the new kernel, things are broken out by board type,
24 Board-specific code::
27 |-- arch
28 | `-- sh
29 | `-- boards
30 | |-- adx
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/openbmc/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2022 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
42 * bits[63:59] - Encode mmap type
43 * bits[45:0] - mmap offset value
48 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
107 * enum hl_mmu_page_table_location - mmu page table location
108 * @MMU_DR_PGT: page-table is located on device DRAM.
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