11da177e4SLinus Torvalds /******************************************************************* 21da177e4SLinus Torvalds * 31da177e4SLinus Torvalds * Copyright (c) 2000 ATecoM GmbH 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * The author may be reached at ecd@atecom.com. 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify it 81da177e4SLinus Torvalds * under the terms of the GNU General Public License as published by the 91da177e4SLinus Torvalds * Free Software Foundation; either version 2 of the License, or (at your 101da177e4SLinus Torvalds * option) any later version. 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 131da177e4SLinus Torvalds * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 141da177e4SLinus Torvalds * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 151da177e4SLinus Torvalds * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 161da177e4SLinus Torvalds * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 171da177e4SLinus Torvalds * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 181da177e4SLinus Torvalds * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 191da177e4SLinus Torvalds * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 201da177e4SLinus Torvalds * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 211da177e4SLinus Torvalds * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 221da177e4SLinus Torvalds * 231da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License along 241da177e4SLinus Torvalds * with this program; if not, write to the Free Software Foundation, Inc., 251da177e4SLinus Torvalds * 675 Mass Ave, Cambridge, MA 02139, USA. 261da177e4SLinus Torvalds * 271da177e4SLinus Torvalds *******************************************************************/ 281da177e4SLinus Torvalds 291da177e4SLinus Torvalds #ifndef _IDT77252_H 301da177e4SLinus Torvalds #define _IDT77252_H 1 311da177e4SLinus Torvalds 321da177e4SLinus Torvalds 331da177e4SLinus Torvalds #include <linux/ptrace.h> 341da177e4SLinus Torvalds #include <linux/skbuff.h> 351da177e4SLinus Torvalds #include <linux/workqueue.h> 367e7a2d07SMatthias Kaehlcke #include <linux/mutex.h> 371da177e4SLinus Torvalds 381da177e4SLinus Torvalds /*****************************************************************************/ 391da177e4SLinus Torvalds /* */ 401da177e4SLinus Torvalds /* Makros */ 411da177e4SLinus Torvalds /* */ 421da177e4SLinus Torvalds /*****************************************************************************/ 431da177e4SLinus Torvalds #define VPCI2VC(card, vpi, vci) \ 441da177e4SLinus Torvalds (((vpi) << card->vcibits) | ((vci) & card->vcimask)) 451da177e4SLinus Torvalds 461da177e4SLinus Torvalds /*****************************************************************************/ 471da177e4SLinus Torvalds /* */ 481da177e4SLinus Torvalds /* DEBUGGING definitions */ 491da177e4SLinus Torvalds /* */ 501da177e4SLinus Torvalds /*****************************************************************************/ 511da177e4SLinus Torvalds 521da177e4SLinus Torvalds #define DBG_RAW_CELL 0x00000400 531da177e4SLinus Torvalds #define DBG_TINY 0x00000200 541da177e4SLinus Torvalds #define DBG_GENERAL 0x00000100 551da177e4SLinus Torvalds #define DBG_XGENERAL 0x00000080 561da177e4SLinus Torvalds #define DBG_INIT 0x00000040 571da177e4SLinus Torvalds #define DBG_DEINIT 0x00000020 581da177e4SLinus Torvalds #define DBG_INTERRUPT 0x00000010 591da177e4SLinus Torvalds #define DBG_OPEN_CONN 0x00000008 601da177e4SLinus Torvalds #define DBG_CLOSE_CONN 0x00000004 611da177e4SLinus Torvalds #define DBG_RX_DATA 0x00000002 621da177e4SLinus Torvalds #define DBG_TX_DATA 0x00000001 631da177e4SLinus Torvalds 641da177e4SLinus Torvalds #ifdef CONFIG_ATM_IDT77252_DEBUG 651da177e4SLinus Torvalds 661da177e4SLinus Torvalds #define CPRINTK(args...) do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0) 671da177e4SLinus Torvalds #define OPRINTK(args...) do { if (debug & DBG_OPEN_CONN) printk(args); } while(0) 681da177e4SLinus Torvalds #define IPRINTK(args...) do { if (debug & DBG_INIT) printk(args); } while(0) 691da177e4SLinus Torvalds #define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT) printk(args); } while(0) 701da177e4SLinus Torvalds #define DIPRINTK(args...) do { if (debug & DBG_DEINIT) printk(args); } while(0) 711da177e4SLinus Torvalds #define TXPRINTK(args...) do { if (debug & DBG_TX_DATA) printk(args); } while(0) 721da177e4SLinus Torvalds #define RXPRINTK(args...) do { if (debug & DBG_RX_DATA) printk(args); } while(0) 731da177e4SLinus Torvalds #define XPRINTK(args...) do { if (debug & DBG_XGENERAL) printk(args); } while(0) 741da177e4SLinus Torvalds #define DPRINTK(args...) do { if (debug & DBG_GENERAL) printk(args); } while(0) 751da177e4SLinus Torvalds #define NPRINTK(args...) do { if (debug & DBG_TINY) printk(args); } while(0) 761da177e4SLinus Torvalds #define RPRINTK(args...) do { if (debug & DBG_RAW_CELL) printk(args); } while(0) 771da177e4SLinus Torvalds 781da177e4SLinus Torvalds #else 791da177e4SLinus Torvalds 801da177e4SLinus Torvalds #define CPRINTK(args...) do { } while(0) 811da177e4SLinus Torvalds #define OPRINTK(args...) do { } while(0) 821da177e4SLinus Torvalds #define IPRINTK(args...) do { } while(0) 831da177e4SLinus Torvalds #define INTPRINTK(args...) do { } while(0) 841da177e4SLinus Torvalds #define DIPRINTK(args...) do { } while(0) 851da177e4SLinus Torvalds #define TXPRINTK(args...) do { } while(0) 861da177e4SLinus Torvalds #define RXPRINTK(args...) do { } while(0) 871da177e4SLinus Torvalds #define XPRINTK(args...) do { } while(0) 881da177e4SLinus Torvalds #define DPRINTK(args...) do { } while(0) 891da177e4SLinus Torvalds #define NPRINTK(args...) do { } while(0) 901da177e4SLinus Torvalds #define RPRINTK(args...) do { } while(0) 911da177e4SLinus Torvalds 921da177e4SLinus Torvalds #endif 931da177e4SLinus Torvalds 941da177e4SLinus Torvalds #define SCHED_UBR0 0 951da177e4SLinus Torvalds #define SCHED_UBR 1 961da177e4SLinus Torvalds #define SCHED_VBR 2 971da177e4SLinus Torvalds #define SCHED_ABR 3 981da177e4SLinus Torvalds #define SCHED_CBR 4 991da177e4SLinus Torvalds 1001da177e4SLinus Torvalds #define SCQFULL_TIMEOUT HZ 1011da177e4SLinus Torvalds 1021da177e4SLinus Torvalds /*****************************************************************************/ 1031da177e4SLinus Torvalds /* */ 1041da177e4SLinus Torvalds /* Free Buffer Queue Layout */ 1051da177e4SLinus Torvalds /* */ 1061da177e4SLinus Torvalds /*****************************************************************************/ 1071da177e4SLinus Torvalds #define SAR_FB_SIZE_0 (2048 - 256) 1081da177e4SLinus Torvalds #define SAR_FB_SIZE_1 (4096 - 256) 1091da177e4SLinus Torvalds #define SAR_FB_SIZE_2 (8192 - 256) 1101da177e4SLinus Torvalds #define SAR_FB_SIZE_3 (16384 - 256) 1111da177e4SLinus Torvalds 1121da177e4SLinus Torvalds #define SAR_FBQ0_LOW 4 1131da177e4SLinus Torvalds #define SAR_FBQ0_HIGH 8 1141da177e4SLinus Torvalds #define SAR_FBQ1_LOW 2 1151da177e4SLinus Torvalds #define SAR_FBQ1_HIGH 4 1161da177e4SLinus Torvalds #define SAR_FBQ2_LOW 1 1171da177e4SLinus Torvalds #define SAR_FBQ2_HIGH 2 1181da177e4SLinus Torvalds #define SAR_FBQ3_LOW 1 1191da177e4SLinus Torvalds #define SAR_FBQ3_HIGH 2 1201da177e4SLinus Torvalds 1211da177e4SLinus Torvalds #if 0 1221da177e4SLinus Torvalds #define SAR_TST_RESERVED 44 /* Num TST reserved for UBR/ABR/VBR */ 1231da177e4SLinus Torvalds #else 1241da177e4SLinus Torvalds #define SAR_TST_RESERVED 0 /* Num TST reserved for UBR/ABR/VBR */ 1251da177e4SLinus Torvalds #endif 1261da177e4SLinus Torvalds 1271da177e4SLinus Torvalds #define TCT_CBR 0x00000000 1281da177e4SLinus Torvalds #define TCT_UBR 0x00000000 1291da177e4SLinus Torvalds #define TCT_VBR 0x40000000 1301da177e4SLinus Torvalds #define TCT_ABR 0x80000000 1311da177e4SLinus Torvalds #define TCT_TYPE 0xc0000000 1321da177e4SLinus Torvalds 1331da177e4SLinus Torvalds #define TCT_RR 0x20000000 1341da177e4SLinus Torvalds #define TCT_LMCR 0x08000000 1351da177e4SLinus Torvalds #define TCT_SCD_MASK 0x0007ffff 1361da177e4SLinus Torvalds 1371da177e4SLinus Torvalds #define TCT_TSIF 0x00004000 1381da177e4SLinus Torvalds #define TCT_HALT 0x80000000 1391da177e4SLinus Torvalds #define TCT_IDLE 0x40000000 1401da177e4SLinus Torvalds #define TCT_FLAG_UBR 0x80000000 1411da177e4SLinus Torvalds 1421da177e4SLinus Torvalds /*****************************************************************************/ 1431da177e4SLinus Torvalds /* */ 1441da177e4SLinus Torvalds /* Structure describing an IDT77252 */ 1451da177e4SLinus Torvalds /* */ 1461da177e4SLinus Torvalds /*****************************************************************************/ 1471da177e4SLinus Torvalds 1481da177e4SLinus Torvalds struct scqe 1491da177e4SLinus Torvalds { 1501da177e4SLinus Torvalds u32 word_1; 1511da177e4SLinus Torvalds u32 word_2; 1521da177e4SLinus Torvalds u32 word_3; 1531da177e4SLinus Torvalds u32 word_4; 1541da177e4SLinus Torvalds }; 1551da177e4SLinus Torvalds 1561da177e4SLinus Torvalds #define SCQ_ENTRIES 64 1571da177e4SLinus Torvalds #define SCQ_SIZE (SCQ_ENTRIES * sizeof(struct scqe)) 1581da177e4SLinus Torvalds #define SCQ_MASK (SCQ_SIZE - 1) 1591da177e4SLinus Torvalds 1601da177e4SLinus Torvalds struct scq_info 1611da177e4SLinus Torvalds { 1621da177e4SLinus Torvalds struct scqe *base; 1631da177e4SLinus Torvalds struct scqe *next; 1641da177e4SLinus Torvalds struct scqe *last; 1651da177e4SLinus Torvalds dma_addr_t paddr; 1661da177e4SLinus Torvalds spinlock_t lock; 1671da177e4SLinus Torvalds atomic_t used; 1681da177e4SLinus Torvalds unsigned long trans_start; 1691da177e4SLinus Torvalds unsigned long scd; 1701da177e4SLinus Torvalds spinlock_t skblock; 1711da177e4SLinus Torvalds struct sk_buff_head transmit; 1721da177e4SLinus Torvalds struct sk_buff_head pending; 1731da177e4SLinus Torvalds }; 1741da177e4SLinus Torvalds 1751da177e4SLinus Torvalds struct rx_pool { 176ceade961SDavid S. Miller struct sk_buff_head queue; 1771da177e4SLinus Torvalds unsigned int len; 1781da177e4SLinus Torvalds }; 1791da177e4SLinus Torvalds 1801da177e4SLinus Torvalds struct aal1 { 1811da177e4SLinus Torvalds unsigned int total; 1821da177e4SLinus Torvalds unsigned int count; 1831da177e4SLinus Torvalds struct sk_buff *data; 1841da177e4SLinus Torvalds unsigned char sequence; 1851da177e4SLinus Torvalds }; 1861da177e4SLinus Torvalds 1873d2ceaa6SKees Cook struct vc_map; 1883d2ceaa6SKees Cook 1891da177e4SLinus Torvalds struct rate_estimator { 1901da177e4SLinus Torvalds struct timer_list timer; 1911da177e4SLinus Torvalds unsigned int interval; 1921da177e4SLinus Torvalds unsigned int ewma_log; 1931da177e4SLinus Torvalds u64 cells; 1941da177e4SLinus Torvalds u64 last_cells; 1951da177e4SLinus Torvalds long avcps; 1961da177e4SLinus Torvalds u32 cps; 1971da177e4SLinus Torvalds u32 maxcps; 1983d2ceaa6SKees Cook struct vc_map *vc; 1991da177e4SLinus Torvalds }; 2001da177e4SLinus Torvalds 2011da177e4SLinus Torvalds struct vc_map { 2021da177e4SLinus Torvalds unsigned int index; 2031da177e4SLinus Torvalds unsigned long flags; 2041da177e4SLinus Torvalds #define VCF_TX 0 2051da177e4SLinus Torvalds #define VCF_RX 1 2061da177e4SLinus Torvalds #define VCF_IDLE 2 2071da177e4SLinus Torvalds #define VCF_RSV 3 2081da177e4SLinus Torvalds unsigned int class; 2091da177e4SLinus Torvalds u8 init_er; 2101da177e4SLinus Torvalds u8 lacr; 2111da177e4SLinus Torvalds u8 max_er; 2121da177e4SLinus Torvalds unsigned int ntste; 2131da177e4SLinus Torvalds spinlock_t lock; 2141da177e4SLinus Torvalds struct atm_vcc *tx_vcc; 2151da177e4SLinus Torvalds struct atm_vcc *rx_vcc; 2161da177e4SLinus Torvalds struct idt77252_dev *card; 2171da177e4SLinus Torvalds struct scq_info *scq; /* To keep track of the SCQ */ 2181da177e4SLinus Torvalds struct rate_estimator *estimator; 2191da177e4SLinus Torvalds int scd_index; 2201da177e4SLinus Torvalds union { 2211da177e4SLinus Torvalds struct rx_pool rx_pool; 2221da177e4SLinus Torvalds struct aal1 aal1; 2231da177e4SLinus Torvalds } rcv; 2241da177e4SLinus Torvalds }; 2251da177e4SLinus Torvalds 2261da177e4SLinus Torvalds /*****************************************************************************/ 2271da177e4SLinus Torvalds /* */ 2281da177e4SLinus Torvalds /* RCTE - Receive Connection Table Entry */ 2291da177e4SLinus Torvalds /* */ 2301da177e4SLinus Torvalds /*****************************************************************************/ 2311da177e4SLinus Torvalds 2321da177e4SLinus Torvalds struct rct_entry 2331da177e4SLinus Torvalds { 2341da177e4SLinus Torvalds u32 word_1; 2351da177e4SLinus Torvalds u32 buffer_handle; 2361da177e4SLinus Torvalds u32 dma_address; 2371da177e4SLinus Torvalds u32 aal5_crc32; 2381da177e4SLinus Torvalds }; 2391da177e4SLinus Torvalds 2401da177e4SLinus Torvalds /*****************************************************************************/ 2411da177e4SLinus Torvalds /* */ 2421da177e4SLinus Torvalds /* RSQ - Receive Status Queue */ 2431da177e4SLinus Torvalds /* */ 2441da177e4SLinus Torvalds /*****************************************************************************/ 2451da177e4SLinus Torvalds 2461da177e4SLinus Torvalds #define SAR_RSQE_VALID 0x80000000 2471da177e4SLinus Torvalds #define SAR_RSQE_IDLE 0x40000000 2481da177e4SLinus Torvalds #define SAR_RSQE_BUF_MASK 0x00030000 2491da177e4SLinus Torvalds #define SAR_RSQE_BUF_ASGN 0x00008000 2501da177e4SLinus Torvalds #define SAR_RSQE_NZGFC 0x00004000 2511da177e4SLinus Torvalds #define SAR_RSQE_EPDU 0x00002000 2521da177e4SLinus Torvalds #define SAR_RSQE_BUF_CONT 0x00001000 2531da177e4SLinus Torvalds #define SAR_RSQE_EFCIE 0x00000800 2541da177e4SLinus Torvalds #define SAR_RSQE_CLP 0x00000400 2551da177e4SLinus Torvalds #define SAR_RSQE_CRC 0x00000200 2561da177e4SLinus Torvalds #define SAR_RSQE_CELLCNT 0x000001FF 2571da177e4SLinus Torvalds 2581da177e4SLinus Torvalds 2591da177e4SLinus Torvalds #define RSQSIZE 8192 2601da177e4SLinus Torvalds #define RSQ_NUM_ENTRIES (RSQSIZE / 16) 2611da177e4SLinus Torvalds #define RSQ_ALIGNMENT 8192 2621da177e4SLinus Torvalds 2631da177e4SLinus Torvalds struct rsq_entry { 2641da177e4SLinus Torvalds u32 word_1; 2651da177e4SLinus Torvalds u32 word_2; 2661da177e4SLinus Torvalds u32 word_3; 2671da177e4SLinus Torvalds u32 word_4; 2681da177e4SLinus Torvalds }; 2691da177e4SLinus Torvalds 2701da177e4SLinus Torvalds struct rsq_info { 2711da177e4SLinus Torvalds struct rsq_entry *base; 2721da177e4SLinus Torvalds struct rsq_entry *next; 2731da177e4SLinus Torvalds struct rsq_entry *last; 2741da177e4SLinus Torvalds dma_addr_t paddr; 2751da177e4SLinus Torvalds }; 2761da177e4SLinus Torvalds 2771da177e4SLinus Torvalds 2781da177e4SLinus Torvalds /*****************************************************************************/ 2791da177e4SLinus Torvalds /* */ 2801da177e4SLinus Torvalds /* TSQ - Transmit Status Queue */ 2811da177e4SLinus Torvalds /* */ 2821da177e4SLinus Torvalds /*****************************************************************************/ 2831da177e4SLinus Torvalds 2841da177e4SLinus Torvalds #define SAR_TSQE_INVALID 0x80000000 2851da177e4SLinus Torvalds #define SAR_TSQE_TIMESTAMP 0x00FFFFFF 2861da177e4SLinus Torvalds #define SAR_TSQE_TYPE 0x60000000 2871da177e4SLinus Torvalds #define SAR_TSQE_TYPE_TIMER 0x00000000 2881da177e4SLinus Torvalds #define SAR_TSQE_TYPE_TSR 0x20000000 2891da177e4SLinus Torvalds #define SAR_TSQE_TYPE_IDLE 0x40000000 2901da177e4SLinus Torvalds #define SAR_TSQE_TYPE_TBD_COMP 0x60000000 2911da177e4SLinus Torvalds 2921da177e4SLinus Torvalds #define SAR_TSQE_TAG(stat) (((stat) >> 24) & 0x1f) 2931da177e4SLinus Torvalds 2941da177e4SLinus Torvalds #define TSQSIZE 8192 2951da177e4SLinus Torvalds #define TSQ_NUM_ENTRIES 1024 2961da177e4SLinus Torvalds #define TSQ_ALIGNMENT 8192 2971da177e4SLinus Torvalds 2981da177e4SLinus Torvalds struct tsq_entry 2991da177e4SLinus Torvalds { 3001da177e4SLinus Torvalds u32 word_1; 3011da177e4SLinus Torvalds u32 word_2; 3021da177e4SLinus Torvalds }; 3031da177e4SLinus Torvalds 3041da177e4SLinus Torvalds struct tsq_info 3051da177e4SLinus Torvalds { 3061da177e4SLinus Torvalds struct tsq_entry *base; 3071da177e4SLinus Torvalds struct tsq_entry *next; 3081da177e4SLinus Torvalds struct tsq_entry *last; 3091da177e4SLinus Torvalds dma_addr_t paddr; 3101da177e4SLinus Torvalds }; 3111da177e4SLinus Torvalds 3121da177e4SLinus Torvalds struct tst_info 3131da177e4SLinus Torvalds { 3141da177e4SLinus Torvalds struct vc_map *vc; 3151da177e4SLinus Torvalds u32 tste; 3161da177e4SLinus Torvalds }; 3171da177e4SLinus Torvalds 3181da177e4SLinus Torvalds #define TSTE_MASK 0x601fffff 3191da177e4SLinus Torvalds 3201da177e4SLinus Torvalds #define TSTE_OPC_MASK 0x60000000 3211da177e4SLinus Torvalds #define TSTE_OPC_NULL 0x00000000 3221da177e4SLinus Torvalds #define TSTE_OPC_CBR 0x20000000 3231da177e4SLinus Torvalds #define TSTE_OPC_VAR 0x40000000 3241da177e4SLinus Torvalds #define TSTE_OPC_JMP 0x60000000 3251da177e4SLinus Torvalds 3261da177e4SLinus Torvalds #define TSTE_PUSH_IDLE 0x01000000 3271da177e4SLinus Torvalds #define TSTE_PUSH_ACTIVE 0x02000000 3281da177e4SLinus Torvalds 3291da177e4SLinus Torvalds #define TST_SWITCH_DONE 0 3301da177e4SLinus Torvalds #define TST_SWITCH_PENDING 1 3311da177e4SLinus Torvalds #define TST_SWITCH_WAIT 2 3321da177e4SLinus Torvalds 3331da177e4SLinus Torvalds #define FBQ_SHIFT 9 3341da177e4SLinus Torvalds #define FBQ_SIZE (1 << FBQ_SHIFT) 3351da177e4SLinus Torvalds #define FBQ_MASK (FBQ_SIZE - 1) 3361da177e4SLinus Torvalds 3371da177e4SLinus Torvalds struct sb_pool 3381da177e4SLinus Torvalds { 3391da177e4SLinus Torvalds unsigned int index; 3401da177e4SLinus Torvalds struct sk_buff *skb[FBQ_SIZE]; 3411da177e4SLinus Torvalds }; 3421da177e4SLinus Torvalds 3431da177e4SLinus Torvalds #define POOL_HANDLE(queue, index) (((queue + 1) << 16) | (index)) 3441da177e4SLinus Torvalds #define POOL_QUEUE(handle) (((handle) >> 16) - 1) 3451da177e4SLinus Torvalds #define POOL_INDEX(handle) ((handle) & 0xffff) 3461da177e4SLinus Torvalds 3471da177e4SLinus Torvalds struct idt77252_dev 3481da177e4SLinus Torvalds { 3491da177e4SLinus Torvalds struct tsq_info tsq; /* Transmit Status Queue */ 3501da177e4SLinus Torvalds struct rsq_info rsq; /* Receive Status Queue */ 3511da177e4SLinus Torvalds 3521da177e4SLinus Torvalds struct pci_dev *pcidev; /* PCI handle (desriptor) */ 3531da177e4SLinus Torvalds struct atm_dev *atmdev; /* ATM device desriptor */ 3541da177e4SLinus Torvalds 3551da177e4SLinus Torvalds void __iomem *membase; /* SAR's memory base address */ 3561da177e4SLinus Torvalds unsigned long srambase; /* SAR's sram base address */ 3571da177e4SLinus Torvalds void __iomem *fbq[4]; /* FBQ fill addresses */ 3581da177e4SLinus Torvalds 3597e7a2d07SMatthias Kaehlcke struct mutex mutex; 3601da177e4SLinus Torvalds spinlock_t cmd_lock; /* for r/w utility/sram */ 3611da177e4SLinus Torvalds 3621da177e4SLinus Torvalds unsigned long softstat; 3631da177e4SLinus Torvalds unsigned long flags; /* see blow */ 3641da177e4SLinus Torvalds 3651da177e4SLinus Torvalds struct work_struct tqueue; 3661da177e4SLinus Torvalds 3671da177e4SLinus Torvalds unsigned long tct_base; /* TCT base address in SRAM */ 3681da177e4SLinus Torvalds unsigned long rct_base; /* RCT base address in SRAM */ 3691da177e4SLinus Torvalds unsigned long rt_base; /* Rate Table base in SRAM */ 3701da177e4SLinus Torvalds unsigned long scd_base; /* SCD base address in SRAM */ 3711da177e4SLinus Torvalds unsigned long tst[2]; /* TST base address in SRAM */ 3721da177e4SLinus Torvalds unsigned long abrst_base; /* ABRST base address in SRAM */ 3731da177e4SLinus Torvalds unsigned long fifo_base; /* RX FIFO base in SRAM */ 3741da177e4SLinus Torvalds 3751da177e4SLinus Torvalds unsigned long irqstat[16]; 3761da177e4SLinus Torvalds 3771da177e4SLinus Torvalds unsigned int sramsize; /* SAR's sram size */ 3781da177e4SLinus Torvalds 3791da177e4SLinus Torvalds unsigned int tct_size; /* total TCT entries */ 3801da177e4SLinus Torvalds unsigned int rct_size; /* total RCT entries */ 3811da177e4SLinus Torvalds unsigned int scd_size; /* length of SCD */ 3821da177e4SLinus Torvalds unsigned int tst_size; /* total TST entries */ 3831da177e4SLinus Torvalds unsigned int tst_free; /* free TSTEs in TST */ 3841da177e4SLinus Torvalds unsigned int abrst_size; /* size of ABRST in words */ 3851da177e4SLinus Torvalds unsigned int fifo_size; /* size of RX FIFO in words */ 3861da177e4SLinus Torvalds 3871da177e4SLinus Torvalds unsigned int vpibits; /* Bits used for VPI index */ 3881da177e4SLinus Torvalds unsigned int vcibits; /* Bits used for VCI index */ 3891da177e4SLinus Torvalds unsigned int vcimask; /* Mask for VCI index */ 3901da177e4SLinus Torvalds 3911da177e4SLinus Torvalds unsigned int utopia_pcr; /* Utopia Itf's Cell Rate */ 3921da177e4SLinus Torvalds unsigned int link_pcr; /* PHY's Peek Cell Rate */ 3931da177e4SLinus Torvalds 3941da177e4SLinus Torvalds struct vc_map **vcs; /* Open Connections */ 3951da177e4SLinus Torvalds struct vc_map **scd2vc; /* SCD to Connection map */ 3961da177e4SLinus Torvalds 3971da177e4SLinus Torvalds struct tst_info *soft_tst; /* TST to Connection map */ 3981da177e4SLinus Torvalds unsigned int tst_index; /* Current TST in use */ 3991da177e4SLinus Torvalds struct timer_list tst_timer; 4001da177e4SLinus Torvalds spinlock_t tst_lock; 4011da177e4SLinus Torvalds unsigned long tst_state; 4021da177e4SLinus Torvalds 4031da177e4SLinus Torvalds struct sb_pool sbpool[4]; /* Pool of RX skbuffs */ 4041da177e4SLinus Torvalds struct sk_buff *raw_cell_head; /* Pointer to raw cell queue */ 4051da177e4SLinus Torvalds u32 *raw_cell_hnd; /* Pointer to RCQ handle */ 4061da177e4SLinus Torvalds dma_addr_t raw_cell_paddr; 4071da177e4SLinus Torvalds 4081da177e4SLinus Torvalds int index; /* SAR's ID */ 4091da177e4SLinus Torvalds int revision; /* chip revision */ 4101da177e4SLinus Torvalds 4111da177e4SLinus Torvalds char name[16]; /* Device name */ 4121da177e4SLinus Torvalds 4131da177e4SLinus Torvalds struct idt77252_dev *next; 4141da177e4SLinus Torvalds }; 4151da177e4SLinus Torvalds 4161da177e4SLinus Torvalds 4171da177e4SLinus Torvalds /* definition for flag field above */ 4181da177e4SLinus Torvalds #define IDT77252_BIT_INIT 1 4191da177e4SLinus Torvalds #define IDT77252_BIT_INTERRUPT 2 4201da177e4SLinus Torvalds 4211da177e4SLinus Torvalds 4221da177e4SLinus Torvalds #define ATM_CELL_PAYLOAD 48 4231da177e4SLinus Torvalds 4241da177e4SLinus Torvalds #define FREEBUF_ALIGNMENT 16 4251da177e4SLinus Torvalds 4261da177e4SLinus Torvalds /*****************************************************************************/ 4271da177e4SLinus Torvalds /* */ 4281da177e4SLinus Torvalds /* Makros */ 4291da177e4SLinus Torvalds /* */ 4301da177e4SLinus Torvalds /*****************************************************************************/ 4311da177e4SLinus Torvalds #define ALIGN_ADDRESS(addr, alignment) \ 4321da177e4SLinus Torvalds ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1)) 4331da177e4SLinus Torvalds 4341da177e4SLinus Torvalds 4351da177e4SLinus Torvalds /*****************************************************************************/ 4361da177e4SLinus Torvalds /* */ 4371da177e4SLinus Torvalds /* ABR SAR Network operation Register */ 4381da177e4SLinus Torvalds /* */ 4391da177e4SLinus Torvalds /*****************************************************************************/ 4401da177e4SLinus Torvalds 4411da177e4SLinus Torvalds #define SAR_REG_DR0 (card->membase + 0x00) 4421da177e4SLinus Torvalds #define SAR_REG_DR1 (card->membase + 0x04) 4431da177e4SLinus Torvalds #define SAR_REG_DR2 (card->membase + 0x08) 4441da177e4SLinus Torvalds #define SAR_REG_DR3 (card->membase + 0x0C) 4451da177e4SLinus Torvalds #define SAR_REG_CMD (card->membase + 0x10) 4461da177e4SLinus Torvalds #define SAR_REG_CFG (card->membase + 0x14) 4471da177e4SLinus Torvalds #define SAR_REG_STAT (card->membase + 0x18) 4481da177e4SLinus Torvalds #define SAR_REG_RSQB (card->membase + 0x1C) 4491da177e4SLinus Torvalds #define SAR_REG_RSQT (card->membase + 0x20) 4501da177e4SLinus Torvalds #define SAR_REG_RSQH (card->membase + 0x24) 4511da177e4SLinus Torvalds #define SAR_REG_CDC (card->membase + 0x28) 4521da177e4SLinus Torvalds #define SAR_REG_VPEC (card->membase + 0x2C) 4531da177e4SLinus Torvalds #define SAR_REG_ICC (card->membase + 0x30) 4541da177e4SLinus Torvalds #define SAR_REG_RAWCT (card->membase + 0x34) 4551da177e4SLinus Torvalds #define SAR_REG_TMR (card->membase + 0x38) 4561da177e4SLinus Torvalds #define SAR_REG_TSTB (card->membase + 0x3C) 4571da177e4SLinus Torvalds #define SAR_REG_TSQB (card->membase + 0x40) 4581da177e4SLinus Torvalds #define SAR_REG_TSQT (card->membase + 0x44) 4591da177e4SLinus Torvalds #define SAR_REG_TSQH (card->membase + 0x48) 4601da177e4SLinus Torvalds #define SAR_REG_GP (card->membase + 0x4C) 4611da177e4SLinus Torvalds #define SAR_REG_VPM (card->membase + 0x50) 4621da177e4SLinus Torvalds #define SAR_REG_RXFD (card->membase + 0x54) 4631da177e4SLinus Torvalds #define SAR_REG_RXFT (card->membase + 0x58) 4641da177e4SLinus Torvalds #define SAR_REG_RXFH (card->membase + 0x5C) 4651da177e4SLinus Torvalds #define SAR_REG_RAWHND (card->membase + 0x60) 4661da177e4SLinus Torvalds #define SAR_REG_RXSTAT (card->membase + 0x64) 4671da177e4SLinus Torvalds #define SAR_REG_ABRSTD (card->membase + 0x68) 4681da177e4SLinus Torvalds #define SAR_REG_ABRRQ (card->membase + 0x6C) 4691da177e4SLinus Torvalds #define SAR_REG_VBRRQ (card->membase + 0x70) 4701da177e4SLinus Torvalds #define SAR_REG_RTBL (card->membase + 0x74) 4711da177e4SLinus Torvalds #define SAR_REG_MDFCT (card->membase + 0x78) 4721da177e4SLinus Torvalds #define SAR_REG_TXSTAT (card->membase + 0x7C) 4731da177e4SLinus Torvalds #define SAR_REG_TCMDQ (card->membase + 0x80) 4741da177e4SLinus Torvalds #define SAR_REG_IRCP (card->membase + 0x84) 4751da177e4SLinus Torvalds #define SAR_REG_FBQP0 (card->membase + 0x88) 4761da177e4SLinus Torvalds #define SAR_REG_FBQP1 (card->membase + 0x8C) 4771da177e4SLinus Torvalds #define SAR_REG_FBQP2 (card->membase + 0x90) 4781da177e4SLinus Torvalds #define SAR_REG_FBQP3 (card->membase + 0x94) 4791da177e4SLinus Torvalds #define SAR_REG_FBQS0 (card->membase + 0x98) 4801da177e4SLinus Torvalds #define SAR_REG_FBQS1 (card->membase + 0x9C) 4811da177e4SLinus Torvalds #define SAR_REG_FBQS2 (card->membase + 0xA0) 4821da177e4SLinus Torvalds #define SAR_REG_FBQS3 (card->membase + 0xA4) 4831da177e4SLinus Torvalds #define SAR_REG_FBQWP0 (card->membase + 0xA8) 4841da177e4SLinus Torvalds #define SAR_REG_FBQWP1 (card->membase + 0xAC) 4851da177e4SLinus Torvalds #define SAR_REG_FBQWP2 (card->membase + 0xB0) 4861da177e4SLinus Torvalds #define SAR_REG_FBQWP3 (card->membase + 0xB4) 4871da177e4SLinus Torvalds #define SAR_REG_NOW (card->membase + 0xB8) 4881da177e4SLinus Torvalds 4891da177e4SLinus Torvalds 4901da177e4SLinus Torvalds /*****************************************************************************/ 4911da177e4SLinus Torvalds /* */ 4921da177e4SLinus Torvalds /* Commands */ 4931da177e4SLinus Torvalds /* */ 4941da177e4SLinus Torvalds /*****************************************************************************/ 4951da177e4SLinus Torvalds 4961da177e4SLinus Torvalds #define SAR_CMD_NO_OPERATION 0x00000000 4971da177e4SLinus Torvalds #define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000 4981da177e4SLinus Torvalds #define SAR_CMD_WRITE_SRAM 0x40000000 4991da177e4SLinus Torvalds #define SAR_CMD_READ_SRAM 0x50000000 5001da177e4SLinus Torvalds #define SAR_CMD_READ_UTILITY 0x80000000 5011da177e4SLinus Torvalds #define SAR_CMD_WRITE_UTILITY 0x90000000 5021da177e4SLinus Torvalds 5031da177e4SLinus Torvalds #define SAR_CMD_OPEN_CONNECTION (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000) 5041da177e4SLinus Torvalds #define SAR_CMD_CLOSE_CONNECTION SAR_CMD_OPENCLOSE_CONNECTION 5051da177e4SLinus Torvalds 5061da177e4SLinus Torvalds 5071da177e4SLinus Torvalds /*****************************************************************************/ 5081da177e4SLinus Torvalds /* */ 5091da177e4SLinus Torvalds /* Configuration Register bits */ 5101da177e4SLinus Torvalds /* */ 5111da177e4SLinus Torvalds /*****************************************************************************/ 5121da177e4SLinus Torvalds 5131da177e4SLinus Torvalds #define SAR_CFG_SWRST 0x80000000 /* Software reset */ 5141da177e4SLinus Torvalds #define SAR_CFG_LOOP 0x40000000 /* Internal Loopback */ 5151da177e4SLinus Torvalds #define SAR_CFG_RXPTH 0x20000000 /* Receive Path Enable */ 5161da177e4SLinus Torvalds #define SAR_CFG_IDLE_CLP 0x10000000 /* SAR set CLP Bits of Null Cells */ 5171da177e4SLinus Torvalds #define SAR_CFG_TX_FIFO_SIZE_1 0x04000000 /* TX FIFO Size = 1 cell */ 5181da177e4SLinus Torvalds #define SAR_CFG_TX_FIFO_SIZE_2 0x08000000 /* TX FIFO Size = 2 cells */ 5191da177e4SLinus Torvalds #define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000 /* TX FIFO Size = 4 cells */ 5201da177e4SLinus Torvalds #define SAR_CFG_TX_FIFO_SIZE_9 0x00000000 /* TX FIFO Size = 9 cells (full) */ 5211da177e4SLinus Torvalds #define SAR_CFG_NO_IDLE 0x02000000 /* SAR sends no Null Cells */ 5221da177e4SLinus Torvalds #define SAR_CFG_RSVD1 0x01000000 /* Reserved */ 5231da177e4SLinus Torvalds #define SAR_CFG_RXSTQ_SIZE_2k 0x00000000 /* RX Stat Queue Size = 2048 byte */ 5241da177e4SLinus Torvalds #define SAR_CFG_RXSTQ_SIZE_4k 0x00400000 /* RX Stat Queue Size = 4096 byte */ 5251da177e4SLinus Torvalds #define SAR_CFG_RXSTQ_SIZE_8k 0x00800000 /* RX Stat Queue Size = 8192 byte */ 5261da177e4SLinus Torvalds #define SAR_CFG_RXSTQ_SIZE_R 0x00C00000 /* RX Stat Queue Size = reserved */ 5271da177e4SLinus Torvalds #define SAR_CFG_ICAPT 0x00200000 /* accept Invalid Cells */ 5281da177e4SLinus Torvalds #define SAR_CFG_IGGFC 0x00100000 /* Ignore GFC */ 5291da177e4SLinus Torvalds #define SAR_CFG_VPVCS_0 0x00000000 /* VPI/VCI Select bit range */ 5301da177e4SLinus Torvalds #define SAR_CFG_VPVCS_1 0x00040000 /* VPI/VCI Select bit range */ 5311da177e4SLinus Torvalds #define SAR_CFG_VPVCS_2 0x00080000 /* VPI/VCI Select bit range */ 5321da177e4SLinus Torvalds #define SAR_CFG_VPVCS_8 0x000C0000 /* VPI/VCI Select bit range */ 5331da177e4SLinus Torvalds #define SAR_CFG_CNTBL_1k 0x00000000 /* Connection Table Size */ 5341da177e4SLinus Torvalds #define SAR_CFG_CNTBL_4k 0x00010000 /* Connection Table Size */ 5351da177e4SLinus Torvalds #define SAR_CFG_CNTBL_16k 0x00020000 /* Connection Table Size */ 5361da177e4SLinus Torvalds #define SAR_CFG_CNTBL_512 0x00030000 /* Connection Table Size */ 5371da177e4SLinus Torvalds #define SAR_CFG_VPECA 0x00008000 /* VPI/VCI Error Cell Accept */ 5381da177e4SLinus Torvalds #define SAR_CFG_RXINT_NOINT 0x00000000 /* No Interrupt on PDU received */ 5391da177e4SLinus Torvalds #define SAR_CFG_RXINT_NODELAY 0x00001000 /* Interrupt without delay to host*/ 5401da177e4SLinus Torvalds #define SAR_CFG_RXINT_256US 0x00002000 /* Interrupt with delay 256 usec */ 5411da177e4SLinus Torvalds #define SAR_CFG_RXINT_505US 0x00003000 /* Interrupt with delay 505 usec */ 5421da177e4SLinus Torvalds #define SAR_CFG_RXINT_742US 0x00004000 /* Interrupt with delay 742 usec */ 5431da177e4SLinus Torvalds #define SAR_CFG_RAWIE 0x00000800 /* Raw Cell Queue Interrupt Enable*/ 5441da177e4SLinus Torvalds #define SAR_CFG_RQFIE 0x00000400 /* RSQ Almost Full Int Enable */ 5451da177e4SLinus Torvalds #define SAR_CFG_RSVD2 0x00000200 /* Reserved */ 5461da177e4SLinus Torvalds #define SAR_CFG_CACHE 0x00000100 /* DMA on Cache Line Boundary */ 5471da177e4SLinus Torvalds #define SAR_CFG_TMOIE 0x00000080 /* Timer Roll Over Int Enable */ 5481da177e4SLinus Torvalds #define SAR_CFG_FBIE 0x00000040 /* Free Buffer Queue Int Enable */ 5491da177e4SLinus Torvalds #define SAR_CFG_TXEN 0x00000020 /* Transmit Operation Enable */ 5501da177e4SLinus Torvalds #define SAR_CFG_TXINT 0x00000010 /* Transmit status Int Enable */ 5511da177e4SLinus Torvalds #define SAR_CFG_TXUIE 0x00000008 /* Transmit underrun Int Enable */ 5521da177e4SLinus Torvalds #define SAR_CFG_UMODE 0x00000004 /* Utopia Mode Select */ 5531da177e4SLinus Torvalds #define SAR_CFG_TXSFI 0x00000002 /* Transmit status Full Int Enable*/ 5541da177e4SLinus Torvalds #define SAR_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */ 5551da177e4SLinus Torvalds 5561da177e4SLinus Torvalds #define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000 /* TX FIFO Size Mask */ 5571da177e4SLinus Torvalds #define SAR_CFG_RXSTQSIZE_MASK 0x00C00000 5581da177e4SLinus Torvalds #define SAR_CFG_CNTBL_MASK 0x00030000 5591da177e4SLinus Torvalds #define SAR_CFG_RXINT_MASK 0x00007000 5601da177e4SLinus Torvalds 5611da177e4SLinus Torvalds 5621da177e4SLinus Torvalds /*****************************************************************************/ 5631da177e4SLinus Torvalds /* */ 5641da177e4SLinus Torvalds /* Status Register bits */ 5651da177e4SLinus Torvalds /* */ 5661da177e4SLinus Torvalds /*****************************************************************************/ 5671da177e4SLinus Torvalds 5681da177e4SLinus Torvalds #define SAR_STAT_FRAC_3 0xF0000000 /* Fraction of Free Buffer Queue 3 */ 5691da177e4SLinus Torvalds #define SAR_STAT_FRAC_2 0x0F000000 /* Fraction of Free Buffer Queue 2 */ 5701da177e4SLinus Torvalds #define SAR_STAT_FRAC_1 0x00F00000 /* Fraction of Free Buffer Queue 1 */ 5711da177e4SLinus Torvalds #define SAR_STAT_FRAC_0 0x000F0000 /* Fraction of Free Buffer Queue 0 */ 5721da177e4SLinus Torvalds #define SAR_STAT_TSIF 0x00008000 /* Transmit Status Indicator */ 5731da177e4SLinus Torvalds #define SAR_STAT_TXICP 0x00004000 /* Transmit Status Indicator */ 5741da177e4SLinus Torvalds #define SAR_STAT_RSVD1 0x00002000 /* Reserved */ 5751da177e4SLinus Torvalds #define SAR_STAT_TSQF 0x00001000 /* Transmit Status Queue full */ 5761da177e4SLinus Torvalds #define SAR_STAT_TMROF 0x00000800 /* Timer overflow */ 5771da177e4SLinus Torvalds #define SAR_STAT_PHYI 0x00000400 /* PHY device Interrupt flag */ 578b595076aSUwe Kleine-König #define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Command Busy Flag */ 5791da177e4SLinus Torvalds #define SAR_STAT_FBQ3A 0x00000100 /* Free Buffer Queue 3 Attention */ 5801da177e4SLinus Torvalds #define SAR_STAT_FBQ2A 0x00000080 /* Free Buffer Queue 2 Attention */ 5811da177e4SLinus Torvalds #define SAR_STAT_RSQF 0x00000040 /* Receive Status Queue full */ 5821da177e4SLinus Torvalds #define SAR_STAT_EPDU 0x00000020 /* End Of PDU Flag */ 5831da177e4SLinus Torvalds #define SAR_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ 5841da177e4SLinus Torvalds #define SAR_STAT_FBQ1A 0x00000008 /* Free Buffer Queue 1 Attention */ 5851da177e4SLinus Torvalds #define SAR_STAT_FBQ0A 0x00000004 /* Free Buffer Queue 0 Attention */ 5861da177e4SLinus Torvalds #define SAR_STAT_RSQAF 0x00000002 /* Receive Status Queue almost full*/ 5871da177e4SLinus Torvalds #define SAR_STAT_RSVD2 0x00000001 /* Reserved */ 5881da177e4SLinus Torvalds 5891da177e4SLinus Torvalds 5901da177e4SLinus Torvalds /*****************************************************************************/ 5911da177e4SLinus Torvalds /* */ 5921da177e4SLinus Torvalds /* General Purpose Register bits */ 5931da177e4SLinus Torvalds /* */ 5941da177e4SLinus Torvalds /*****************************************************************************/ 5951da177e4SLinus Torvalds 5961da177e4SLinus Torvalds #define SAR_GP_TXNCC_MASK 0xff000000 /* Transmit Negative Credit Count */ 5971da177e4SLinus Torvalds #define SAR_GP_EEDI 0x00010000 /* EEPROM Data In */ 5981da177e4SLinus Torvalds #define SAR_GP_BIGE 0x00008000 /* Big Endian Operation */ 5991da177e4SLinus Torvalds #define SAR_GP_RM_NORMAL 0x00000000 /* Normal handling of RM cells */ 6001da177e4SLinus Torvalds #define SAR_GP_RM_TO_RCQ 0x00002000 /* put RM cells into Raw Cell Queue */ 6011da177e4SLinus Torvalds #define SAR_GP_RM_RSVD 0x00004000 /* Reserved */ 6021da177e4SLinus Torvalds #define SAR_GP_RM_INHIBIT 0x00006000 /* Inhibit update of Connection tab */ 6031da177e4SLinus Torvalds #define SAR_GP_PHY_RESET 0x00000008 /* PHY Reset */ 6041da177e4SLinus Torvalds #define SAR_GP_EESCLK 0x00000004 /* EEPROM SCLK */ 6051da177e4SLinus Torvalds #define SAR_GP_EECS 0x00000002 /* EEPROM Chip Select */ 6061da177e4SLinus Torvalds #define SAR_GP_EEDO 0x00000001 /* EEPROM Data Out */ 6071da177e4SLinus Torvalds 6081da177e4SLinus Torvalds 6091da177e4SLinus Torvalds /*****************************************************************************/ 6101da177e4SLinus Torvalds /* */ 6111da177e4SLinus Torvalds /* SAR local SRAM layout for 128k work SRAM */ 6121da177e4SLinus Torvalds /* */ 6131da177e4SLinus Torvalds /*****************************************************************************/ 6141da177e4SLinus Torvalds 6151da177e4SLinus Torvalds #define SAR_SRAM_SCD_SIZE 12 6161da177e4SLinus Torvalds #define SAR_SRAM_TCT_SIZE 8 6171da177e4SLinus Torvalds #define SAR_SRAM_RCT_SIZE 4 6181da177e4SLinus Torvalds 6191da177e4SLinus Torvalds #define SAR_SRAM_TCT_128_BASE 0x00000 6201da177e4SLinus Torvalds #define SAR_SRAM_TCT_128_TOP 0x01fff 6211da177e4SLinus Torvalds #define SAR_SRAM_RCT_128_BASE 0x02000 6221da177e4SLinus Torvalds #define SAR_SRAM_RCT_128_TOP 0x02fff 6231da177e4SLinus Torvalds #define SAR_SRAM_FB0_128_BASE 0x03000 6241da177e4SLinus Torvalds #define SAR_SRAM_FB0_128_TOP 0x033ff 6251da177e4SLinus Torvalds #define SAR_SRAM_FB1_128_BASE 0x03400 6261da177e4SLinus Torvalds #define SAR_SRAM_FB1_128_TOP 0x037ff 6271da177e4SLinus Torvalds #define SAR_SRAM_FB2_128_BASE 0x03800 6281da177e4SLinus Torvalds #define SAR_SRAM_FB2_128_TOP 0x03bff 6291da177e4SLinus Torvalds #define SAR_SRAM_FB3_128_BASE 0x03c00 6301da177e4SLinus Torvalds #define SAR_SRAM_FB3_128_TOP 0x03fff 6311da177e4SLinus Torvalds #define SAR_SRAM_SCD_128_BASE 0x04000 6321da177e4SLinus Torvalds #define SAR_SRAM_SCD_128_TOP 0x07fff 6331da177e4SLinus Torvalds #define SAR_SRAM_TST1_128_BASE 0x08000 6341da177e4SLinus Torvalds #define SAR_SRAM_TST1_128_TOP 0x0bfff 6351da177e4SLinus Torvalds #define SAR_SRAM_TST2_128_BASE 0x0c000 6361da177e4SLinus Torvalds #define SAR_SRAM_TST2_128_TOP 0x0ffff 6371da177e4SLinus Torvalds #define SAR_SRAM_ABRSTD_128_BASE 0x10000 6381da177e4SLinus Torvalds #define SAR_SRAM_ABRSTD_128_TOP 0x13fff 6391da177e4SLinus Torvalds #define SAR_SRAM_RT_128_BASE 0x14000 6401da177e4SLinus Torvalds #define SAR_SRAM_RT_128_TOP 0x15fff 6411da177e4SLinus Torvalds 6421da177e4SLinus Torvalds #define SAR_SRAM_FIFO_128_BASE 0x18000 6431da177e4SLinus Torvalds #define SAR_SRAM_FIFO_128_TOP 0x1ffff 6441da177e4SLinus Torvalds 6451da177e4SLinus Torvalds 6461da177e4SLinus Torvalds /*****************************************************************************/ 6471da177e4SLinus Torvalds /* */ 6481da177e4SLinus Torvalds /* SAR local SRAM layout for 32k work SRAM */ 6491da177e4SLinus Torvalds /* */ 6501da177e4SLinus Torvalds /*****************************************************************************/ 6511da177e4SLinus Torvalds 6521da177e4SLinus Torvalds #define SAR_SRAM_TCT_32_BASE 0x00000 6531da177e4SLinus Torvalds #define SAR_SRAM_TCT_32_TOP 0x00fff 6541da177e4SLinus Torvalds #define SAR_SRAM_RCT_32_BASE 0x01000 6551da177e4SLinus Torvalds #define SAR_SRAM_RCT_32_TOP 0x017ff 6561da177e4SLinus Torvalds #define SAR_SRAM_FB0_32_BASE 0x01800 6571da177e4SLinus Torvalds #define SAR_SRAM_FB0_32_TOP 0x01bff 6581da177e4SLinus Torvalds #define SAR_SRAM_FB1_32_BASE 0x01c00 6591da177e4SLinus Torvalds #define SAR_SRAM_FB1_32_TOP 0x01fff 6601da177e4SLinus Torvalds #define SAR_SRAM_FB2_32_BASE 0x02000 6611da177e4SLinus Torvalds #define SAR_SRAM_FB2_32_TOP 0x023ff 6621da177e4SLinus Torvalds #define SAR_SRAM_FB3_32_BASE 0x02400 6631da177e4SLinus Torvalds #define SAR_SRAM_FB3_32_TOP 0x027ff 6641da177e4SLinus Torvalds #define SAR_SRAM_SCD_32_BASE 0x02800 6651da177e4SLinus Torvalds #define SAR_SRAM_SCD_32_TOP 0x03fff 6661da177e4SLinus Torvalds #define SAR_SRAM_TST1_32_BASE 0x04000 6671da177e4SLinus Torvalds #define SAR_SRAM_TST1_32_TOP 0x04fff 6681da177e4SLinus Torvalds #define SAR_SRAM_TST2_32_BASE 0x05000 6691da177e4SLinus Torvalds #define SAR_SRAM_TST2_32_TOP 0x05fff 6701da177e4SLinus Torvalds #define SAR_SRAM_ABRSTD_32_BASE 0x06000 6711da177e4SLinus Torvalds #define SAR_SRAM_ABRSTD_32_TOP 0x067ff 6721da177e4SLinus Torvalds #define SAR_SRAM_RT_32_BASE 0x06800 6731da177e4SLinus Torvalds #define SAR_SRAM_RT_32_TOP 0x06fff 6741da177e4SLinus Torvalds #define SAR_SRAM_FIFO_32_BASE 0x07000 6751da177e4SLinus Torvalds #define SAR_SRAM_FIFO_32_TOP 0x07fff 6761da177e4SLinus Torvalds 6771da177e4SLinus Torvalds 6781da177e4SLinus Torvalds /*****************************************************************************/ 6791da177e4SLinus Torvalds /* */ 6801da177e4SLinus Torvalds /* TSR - Transmit Status Request */ 6811da177e4SLinus Torvalds /* */ 6821da177e4SLinus Torvalds /*****************************************************************************/ 6831da177e4SLinus Torvalds 6841da177e4SLinus Torvalds #define SAR_TSR_TYPE_TSR 0x80000000 6851da177e4SLinus Torvalds #define SAR_TSR_TYPE_TBD 0x00000000 6861da177e4SLinus Torvalds #define SAR_TSR_TSIF 0x20000000 6871da177e4SLinus Torvalds #define SAR_TSR_TAG_MASK 0x01F00000 6881da177e4SLinus Torvalds 6891da177e4SLinus Torvalds 6901da177e4SLinus Torvalds /*****************************************************************************/ 6911da177e4SLinus Torvalds /* */ 6921da177e4SLinus Torvalds /* TBD - Transmit Buffer Descriptor */ 6931da177e4SLinus Torvalds /* */ 6941da177e4SLinus Torvalds /*****************************************************************************/ 6951da177e4SLinus Torvalds 6961da177e4SLinus Torvalds #define SAR_TBD_EPDU 0x40000000 6971da177e4SLinus Torvalds #define SAR_TBD_TSIF 0x20000000 6981da177e4SLinus Torvalds #define SAR_TBD_OAM 0x10000000 6991da177e4SLinus Torvalds #define SAR_TBD_AAL0 0x00000000 7001da177e4SLinus Torvalds #define SAR_TBD_AAL34 0x04000000 7011da177e4SLinus Torvalds #define SAR_TBD_AAL5 0x08000000 7021da177e4SLinus Torvalds #define SAR_TBD_GTSI 0x02000000 7031da177e4SLinus Torvalds #define SAR_TBD_TAG_MASK 0x01F00000 7041da177e4SLinus Torvalds 7051da177e4SLinus Torvalds #define SAR_TBD_VPI_MASK 0x0FF00000 7061da177e4SLinus Torvalds #define SAR_TBD_VCI_MASK 0x000FFFF0 7071da177e4SLinus Torvalds #define SAR_TBD_VC_MASK (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK) 7081da177e4SLinus Torvalds 7091da177e4SLinus Torvalds #define SAR_TBD_VPI_SHIFT 20 7101da177e4SLinus Torvalds #define SAR_TBD_VCI_SHIFT 4 7111da177e4SLinus Torvalds 7121da177e4SLinus Torvalds 7131da177e4SLinus Torvalds /*****************************************************************************/ 7141da177e4SLinus Torvalds /* */ 7151da177e4SLinus Torvalds /* RXFD - Receive FIFO Descriptor */ 7161da177e4SLinus Torvalds /* */ 7171da177e4SLinus Torvalds /*****************************************************************************/ 7181da177e4SLinus Torvalds 7191da177e4SLinus Torvalds #define SAR_RXFD_SIZE_MASK 0x0F000000 7201da177e4SLinus Torvalds #define SAR_RXFD_SIZE_512 0x00000000 /* 512 words */ 7211da177e4SLinus Torvalds #define SAR_RXFD_SIZE_1K 0x01000000 /* 1k words */ 7221da177e4SLinus Torvalds #define SAR_RXFD_SIZE_2K 0x02000000 /* 2k words */ 7231da177e4SLinus Torvalds #define SAR_RXFD_SIZE_4K 0x03000000 /* 4k words */ 7241da177e4SLinus Torvalds #define SAR_RXFD_SIZE_8K 0x04000000 /* 8k words */ 7251da177e4SLinus Torvalds #define SAR_RXFD_SIZE_16K 0x05000000 /* 16k words */ 7261da177e4SLinus Torvalds #define SAR_RXFD_SIZE_32K 0x06000000 /* 32k words */ 7271da177e4SLinus Torvalds #define SAR_RXFD_SIZE_64K 0x07000000 /* 64k words */ 7281da177e4SLinus Torvalds #define SAR_RXFD_SIZE_128K 0x08000000 /* 128k words */ 7291da177e4SLinus Torvalds #define SAR_RXFD_SIZE_256K 0x09000000 /* 256k words */ 7301da177e4SLinus Torvalds #define SAR_RXFD_ADDR_MASK 0x001ffc00 7311da177e4SLinus Torvalds 7321da177e4SLinus Torvalds 7331da177e4SLinus Torvalds /*****************************************************************************/ 7341da177e4SLinus Torvalds /* */ 7351da177e4SLinus Torvalds /* ABRSTD - ABR + VBR Schedule Tables */ 7361da177e4SLinus Torvalds /* */ 7371da177e4SLinus Torvalds /*****************************************************************************/ 7381da177e4SLinus Torvalds 7391da177e4SLinus Torvalds #define SAR_ABRSTD_SIZE_MASK 0x07000000 7401da177e4SLinus Torvalds #define SAR_ABRSTD_SIZE_512 0x00000000 /* 512 words */ 7411da177e4SLinus Torvalds #define SAR_ABRSTD_SIZE_1K 0x01000000 /* 1k words */ 7421da177e4SLinus Torvalds #define SAR_ABRSTD_SIZE_2K 0x02000000 /* 2k words */ 7431da177e4SLinus Torvalds #define SAR_ABRSTD_SIZE_4K 0x03000000 /* 4k words */ 7441da177e4SLinus Torvalds #define SAR_ABRSTD_SIZE_8K 0x04000000 /* 8k words */ 7451da177e4SLinus Torvalds #define SAR_ABRSTD_SIZE_16K 0x05000000 /* 16k words */ 7461da177e4SLinus Torvalds #define SAR_ABRSTD_ADDR_MASK 0x001ffc00 7471da177e4SLinus Torvalds 7481da177e4SLinus Torvalds 7491da177e4SLinus Torvalds /*****************************************************************************/ 7501da177e4SLinus Torvalds /* */ 7511da177e4SLinus Torvalds /* RCTE - Receive Connection Table Entry */ 7521da177e4SLinus Torvalds /* */ 7531da177e4SLinus Torvalds /*****************************************************************************/ 7541da177e4SLinus Torvalds 7551da177e4SLinus Torvalds #define SAR_RCTE_IL_MASK 0xE0000000 /* inactivity limit */ 7561da177e4SLinus Torvalds #define SAR_RCTE_IC_MASK 0x1C000000 /* inactivity count */ 7571da177e4SLinus Torvalds #define SAR_RCTE_RSVD 0x02000000 /* reserved */ 7581da177e4SLinus Torvalds #define SAR_RCTE_LCD 0x01000000 /* last cell data */ 7591da177e4SLinus Torvalds #define SAR_RCTE_CI_VC 0x00800000 /* EFCI in previous cell of VC */ 7601da177e4SLinus Torvalds #define SAR_RCTE_FBP_01 0x00000000 /* 1. cell->FBQ0, others->FBQ1 */ 7611da177e4SLinus Torvalds #define SAR_RCTE_FBP_1 0x00200000 /* use FBQ 1 for all cells */ 7621da177e4SLinus Torvalds #define SAR_RCTE_FBP_2 0x00400000 /* use FBQ 2 for all cells */ 7631da177e4SLinus Torvalds #define SAR_RCTE_FBP_3 0x00600000 /* use FBQ 3 for all cells */ 7641da177e4SLinus Torvalds #define SAR_RCTE_NZ_GFC 0x00100000 /* non zero GFC in all cell of VC */ 7651da177e4SLinus Torvalds #define SAR_RCTE_CONNECTOPEN 0x00080000 /* VC is open */ 7661da177e4SLinus Torvalds #define SAR_RCTE_AAL_MASK 0x00070000 /* mask for AAL type field s.b. */ 7671da177e4SLinus Torvalds #define SAR_RCTE_RAWCELLINTEN 0x00008000 /* raw cell interrupt enable */ 7681da177e4SLinus Torvalds #define SAR_RCTE_RXCONCELLADDR 0x00004000 /* RX constant cell address */ 7691da177e4SLinus Torvalds #define SAR_RCTE_BUFFSTAT_MASK 0x00003000 /* buffer status */ 7701da177e4SLinus Torvalds #define SAR_RCTE_EFCI 0x00000800 /* EFCI Congestion flag */ 7711da177e4SLinus Torvalds #define SAR_RCTE_CLP 0x00000400 /* Cell Loss Priority flag */ 77225985edcSLucas De Marchi #define SAR_RCTE_CRC 0x00000200 /* Received CRC Error */ 7731da177e4SLinus Torvalds #define SAR_RCTE_CELLCNT_MASK 0x000001FF /* cell Count */ 7741da177e4SLinus Torvalds 7751da177e4SLinus Torvalds #define SAR_RCTE_AAL0 0x00000000 /* AAL types for ALL field */ 7761da177e4SLinus Torvalds #define SAR_RCTE_AAL34 0x00010000 7771da177e4SLinus Torvalds #define SAR_RCTE_AAL5 0x00020000 7781da177e4SLinus Torvalds #define SAR_RCTE_RCQ 0x00030000 7791da177e4SLinus Torvalds #define SAR_RCTE_OAM 0x00040000 7801da177e4SLinus Torvalds 7811da177e4SLinus Torvalds #define TCMDQ_START 0x01000000 7821da177e4SLinus Torvalds #define TCMDQ_LACR 0x02000000 7831da177e4SLinus Torvalds #define TCMDQ_START_LACR 0x03000000 7841da177e4SLinus Torvalds #define TCMDQ_INIT_ER 0x04000000 7851da177e4SLinus Torvalds #define TCMDQ_HALT 0x05000000 7861da177e4SLinus Torvalds 7871da177e4SLinus Torvalds 7881da177e4SLinus Torvalds struct idt77252_skb_prv { 7891da177e4SLinus Torvalds struct scqe tbd; /* Transmit Buffer Descriptor */ 7901da177e4SLinus Torvalds dma_addr_t paddr; /* DMA handle */ 7911da177e4SLinus Torvalds u32 pool; /* sb_pool handle */ 792*d0a0bbe7STong Zhang } __packed; 7931da177e4SLinus Torvalds 7941da177e4SLinus Torvalds #define IDT77252_PRV_TBD(skb) \ 7951da177e4SLinus Torvalds (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd) 7961da177e4SLinus Torvalds #define IDT77252_PRV_PADDR(skb) \ 7971da177e4SLinus Torvalds (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr) 7981da177e4SLinus Torvalds #define IDT77252_PRV_POOL(skb) \ 7991da177e4SLinus Torvalds (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool) 8001da177e4SLinus Torvalds 8011da177e4SLinus Torvalds /*****************************************************************************/ 8021da177e4SLinus Torvalds /* */ 8031da177e4SLinus Torvalds /* PCI related items */ 8041da177e4SLinus Torvalds /* */ 8051da177e4SLinus Torvalds /*****************************************************************************/ 8061da177e4SLinus Torvalds 8071da177e4SLinus Torvalds #ifndef PCI_VENDOR_ID_IDT 8081da177e4SLinus Torvalds #define PCI_VENDOR_ID_IDT 0x111D 8091da177e4SLinus Torvalds #endif /* PCI_VENDOR_ID_IDT */ 8101da177e4SLinus Torvalds 8111da177e4SLinus Torvalds #ifndef PCI_DEVICE_ID_IDT_IDT77252 8121da177e4SLinus Torvalds #define PCI_DEVICE_ID_IDT_IDT77252 0x0003 8131da177e4SLinus Torvalds #endif /* PCI_DEVICE_ID_IDT_IDT772052 */ 8141da177e4SLinus Torvalds 8151da177e4SLinus Torvalds 8161da177e4SLinus Torvalds #endif /* !(_IDT77252_H) */ 817