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Searched +full:spi +full:- +full:src +full:- +full:clk (Results 1 – 23 of 23) sorted by relevance

/openbmc/u-boot/drivers/spi/
H A Dpic32_spi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Microchip PIC32 SPI controller driver.
10 #include <clk.h>
14 #include <spi.h>
19 #include <dt-bindings/clock/microchip,clock.h>
24 /* PIC32 SPI controller registers */
33 /* Bit fields in SPI Control Register */
34 #define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
45 #define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
46 #define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
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/openbmc/u-boot/arch/arm/dts/
H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
14 cpu-model = "Exynos5800";
16 compatible = "google,pit-rev#", "google,pit",
20 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
21 hwid = "PIT TEST A-A 7848";
22 lazy-init = <1>;
33 compatible = "pwm-backlight";
35 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
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H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
34 compatible = "pwm-backlight";
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H A Dam57xx-idk-common.dtsi2 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
9 #include "am57xx-industrial-grade.dtsi"
18 stdout-path = &uart3;
21 vmain: fixedregulator-vmain {
22 compatible = "regulator-fixed";
23 regulator-name = "VMAIN";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 regulator-always-on;
27 regulator-boot-on;
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H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3128-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
42 arm-pmu {
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H A Dr8a7790.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7790-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
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H A Dr8a7791.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7791-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
45 compatible = "fixed-clock";
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H A Dr8a7796.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
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H A Dr8a7793.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
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H A Dr8a7795.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
42 compatible = "fixed-clock";
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H A Dr8a7794.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7794-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
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H A Dr8a77965.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h>
19 #address-cells = <2>;
20 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 compatible = "fixed-clock";
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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Intel Corporation
10 #include <clk.h>
11 #include <dm/device-internal.h>
80 { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
81 { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
82 { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
83 { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
84 { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
85 { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
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H A Dclock_manager_gen5.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
21 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
28 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
53 * Put peripheral and main pll src to reset value to avoid glitch.
82 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
83 &clock_manager_base->per_pll.en); in cm_basic_init()
92 &clock_manager_base->main_pll.en); in cm_basic_init()
94 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
97 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
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/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3399-cru.h>
41 ((input_rate) / (output_rate) - 1);
234 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
238 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
306 * FOUTVCO = Fractional PLL non-divided output frequency
317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
318 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
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/openbmc/u-boot/cmd/
H A DKconfig4 bool "Support U-Boot commands"
7 Enable U-Boot's command-line functions. This provides a means
8 to enter commands into U-Boot for a wide variety of purposes. It
12 substantially to the size of U-Boot.
71 U-Boot automatic booting process and bring the device
72 to the U-Boot prompt for user input.
103 autoboot starts booting, U-Boot gives a command prompt. The
104 U-Boot prompt will time out if CONFIG_BOOT_RETRY_TIME is
116 U-Boot gives a command prompt. The U-Boot prompt never
120 bool "Enable Ctrl-C autoboot interruption"
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/openbmc/u-boot/board/congatec/cgtqmx6eval/
H A Dcgtqmx6eval.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
6 * Leo Sartre, <lsartre@adeneo-embedded.com>
12 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/sata.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/mxc_i2c.h>
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/openbmc/u-boot/board/phytec/pcm058/
H A Dpcm058.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/mx6-ddr.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/mach-imx/spi.h>
70 gd->ram_size = imx_ddr_size(); in dram_init()
183 return devno - 1; in board_mmc_get_env_dev()
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/openbmc/u-boot/lib/
H A Dfdtdec.c1 // SPDX-License-Identifier: GPL-2.0+
30 * good reason why driver-model conversion is infeasible. Examples include
36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
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/openbmc/u-boot/board/freescale/mx6sabresd/
H A Dmx6sabresd.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/mach-imx/spi.h>
15 #include <asm/mach-imx/mxc_i2c.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/video.h>
33 #include <usb/ehci-ci.h>
65 gd->ram_size = imx_ddr_size(); in dram_init()
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/openbmc/
Dopengrok1.0.log1 2025-12-13 03:01:08.597-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-13 03:01:08.672-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src,
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Dopengrok2.0.log1 2025-12-12 03:01:08.265-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-12 03:01:08.342-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src,
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/openbmc/qemu/tests/data/qobject/
H A Dqdict.txt1 00-INDEX: 333
55 3.Early-stage: 9993
56 3w-9xxx.c: 77318
57 3w-9xxx.h: 26357
58 3w-xxxx.c: 85227
59 3w-xxxx.h: 16846
71 4level-fixup.h: 1028
110 6xx-suspend.S: 1086
148 8250-platform.c: 1091
161 83xx-512x-pci.txt: 1323
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