1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2e19b9004SPurna Chandra Mandal /*
3e19b9004SPurna Chandra Mandal * Microchip PIC32 SPI controller driver.
4e19b9004SPurna Chandra Mandal *
5e19b9004SPurna Chandra Mandal * Copyright (c) 2015, Microchip Technology Inc.
6e19b9004SPurna Chandra Mandal * Purna Chandra Mandal <purna.mandal@microchip.com>
7e19b9004SPurna Chandra Mandal */
8e19b9004SPurna Chandra Mandal
9e19b9004SPurna Chandra Mandal #include <common.h>
10e19b9004SPurna Chandra Mandal #include <clk.h>
11e19b9004SPurna Chandra Mandal #include <dm.h>
12e19b9004SPurna Chandra Mandal #include <linux/compat.h>
13e19b9004SPurna Chandra Mandal #include <malloc.h>
14e19b9004SPurna Chandra Mandal #include <spi.h>
15e19b9004SPurna Chandra Mandal
16e19b9004SPurna Chandra Mandal #include <asm/types.h>
17e19b9004SPurna Chandra Mandal #include <asm/io.h>
18e19b9004SPurna Chandra Mandal #include <asm/gpio.h>
19e19b9004SPurna Chandra Mandal #include <dt-bindings/clock/microchip,clock.h>
20e19b9004SPurna Chandra Mandal #include <mach/pic32.h>
21e19b9004SPurna Chandra Mandal
22e19b9004SPurna Chandra Mandal DECLARE_GLOBAL_DATA_PTR;
23e19b9004SPurna Chandra Mandal
24e19b9004SPurna Chandra Mandal /* PIC32 SPI controller registers */
25e19b9004SPurna Chandra Mandal struct pic32_reg_spi {
26e19b9004SPurna Chandra Mandal struct pic32_reg_atomic ctrl;
27e19b9004SPurna Chandra Mandal struct pic32_reg_atomic status;
28e19b9004SPurna Chandra Mandal struct pic32_reg_atomic buf;
29e19b9004SPurna Chandra Mandal struct pic32_reg_atomic baud;
30e19b9004SPurna Chandra Mandal struct pic32_reg_atomic ctrl2;
31e19b9004SPurna Chandra Mandal };
32e19b9004SPurna Chandra Mandal
33e19b9004SPurna Chandra Mandal /* Bit fields in SPI Control Register */
34e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
35e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
36e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
37e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
38e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
39e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_BPW_8 0x0
40e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_BPW_16 0x1
41e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_BPW_32 0x2
42e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_BPW_SHIFT 10
43e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
44e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
45e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
46e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
47e19b9004SPurna Chandra Mandal #define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
48e19b9004SPurna Chandra Mandal
49e19b9004SPurna Chandra Mandal /* Bit fields in SPI Status Register */
50e19b9004SPurna Chandra Mandal #define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
51e19b9004SPurna Chandra Mandal #define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
52e19b9004SPurna Chandra Mandal #define PIC32_SPI_STAT_TF_LVL_SHIFT 16
53e19b9004SPurna Chandra Mandal #define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
54e19b9004SPurna Chandra Mandal #define PIC32_SPI_STAT_RF_LVL_SHIFT 24
55e19b9004SPurna Chandra Mandal
56e19b9004SPurna Chandra Mandal /* Bit fields in SPI Baud Register */
57e19b9004SPurna Chandra Mandal #define PIC32_SPI_BAUD_MASK 0x1ff
58e19b9004SPurna Chandra Mandal
59e19b9004SPurna Chandra Mandal struct pic32_spi_priv {
60e19b9004SPurna Chandra Mandal struct pic32_reg_spi *regs;
61e19b9004SPurna Chandra Mandal u32 fifo_depth; /* FIFO depth in bytes */
62e19b9004SPurna Chandra Mandal u32 fifo_n_word; /* FIFO depth in words */
63e19b9004SPurna Chandra Mandal struct gpio_desc cs_gpio;
64e19b9004SPurna Chandra Mandal
65e19b9004SPurna Chandra Mandal /* Current SPI slave specific */
66e19b9004SPurna Chandra Mandal ulong clk_rate;
67e19b9004SPurna Chandra Mandal u32 speed_hz; /* spi-clk rate */
68e19b9004SPurna Chandra Mandal int mode;
69e19b9004SPurna Chandra Mandal
70e19b9004SPurna Chandra Mandal /* Current message/transfer state */
71e19b9004SPurna Chandra Mandal const void *tx;
72e19b9004SPurna Chandra Mandal const void *tx_end;
73e19b9004SPurna Chandra Mandal const void *rx;
74e19b9004SPurna Chandra Mandal const void *rx_end;
75e19b9004SPurna Chandra Mandal u32 len;
76e19b9004SPurna Chandra Mandal
77e19b9004SPurna Chandra Mandal /* SPI FiFo accessor */
78e19b9004SPurna Chandra Mandal void (*rx_fifo)(struct pic32_spi_priv *);
79e19b9004SPurna Chandra Mandal void (*tx_fifo)(struct pic32_spi_priv *);
80e19b9004SPurna Chandra Mandal };
81e19b9004SPurna Chandra Mandal
pic32_spi_enable(struct pic32_spi_priv * priv)82e19b9004SPurna Chandra Mandal static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
83e19b9004SPurna Chandra Mandal {
84e19b9004SPurna Chandra Mandal writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
85e19b9004SPurna Chandra Mandal }
86e19b9004SPurna Chandra Mandal
pic32_spi_disable(struct pic32_spi_priv * priv)87e19b9004SPurna Chandra Mandal static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
88e19b9004SPurna Chandra Mandal {
89e19b9004SPurna Chandra Mandal writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
90e19b9004SPurna Chandra Mandal }
91e19b9004SPurna Chandra Mandal
pic32_spi_rx_fifo_level(struct pic32_spi_priv * priv)92e19b9004SPurna Chandra Mandal static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
93e19b9004SPurna Chandra Mandal {
94e19b9004SPurna Chandra Mandal u32 sr = readl(&priv->regs->status.raw);
95e19b9004SPurna Chandra Mandal
96e19b9004SPurna Chandra Mandal return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
97e19b9004SPurna Chandra Mandal }
98e19b9004SPurna Chandra Mandal
pic32_spi_tx_fifo_level(struct pic32_spi_priv * priv)99e19b9004SPurna Chandra Mandal static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
100e19b9004SPurna Chandra Mandal {
101e19b9004SPurna Chandra Mandal u32 sr = readl(&priv->regs->status.raw);
102e19b9004SPurna Chandra Mandal
103e19b9004SPurna Chandra Mandal return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
104e19b9004SPurna Chandra Mandal }
105e19b9004SPurna Chandra Mandal
106e19b9004SPurna Chandra Mandal /* Return the max entries we can fill into tx fifo */
pic32_tx_max(struct pic32_spi_priv * priv,int n_bytes)107e19b9004SPurna Chandra Mandal static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
108e19b9004SPurna Chandra Mandal {
109e19b9004SPurna Chandra Mandal u32 tx_left, tx_room, rxtx_gap;
110e19b9004SPurna Chandra Mandal
111e19b9004SPurna Chandra Mandal tx_left = (priv->tx_end - priv->tx) / n_bytes;
112e19b9004SPurna Chandra Mandal tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
113e19b9004SPurna Chandra Mandal
114e19b9004SPurna Chandra Mandal rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
115e19b9004SPurna Chandra Mandal rxtx_gap /= n_bytes;
116e19b9004SPurna Chandra Mandal return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
117e19b9004SPurna Chandra Mandal }
118e19b9004SPurna Chandra Mandal
119e19b9004SPurna Chandra Mandal /* Return the max entries we should read out of rx fifo */
pic32_rx_max(struct pic32_spi_priv * priv,int n_bytes)120e19b9004SPurna Chandra Mandal static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
121e19b9004SPurna Chandra Mandal {
122e19b9004SPurna Chandra Mandal u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
123e19b9004SPurna Chandra Mandal
124e19b9004SPurna Chandra Mandal return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
125e19b9004SPurna Chandra Mandal }
126e19b9004SPurna Chandra Mandal
127e19b9004SPurna Chandra Mandal #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
128e19b9004SPurna Chandra Mandal static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
129e19b9004SPurna Chandra Mandal { \
130e19b9004SPurna Chandra Mandal __type val; \
131e19b9004SPurna Chandra Mandal u32 mx = pic32_rx_max(priv, sizeof(__type)); \
132e19b9004SPurna Chandra Mandal \
133e19b9004SPurna Chandra Mandal for (; mx; mx--) { \
134e19b9004SPurna Chandra Mandal val = read##__bwl(&priv->regs->buf.raw); \
135e19b9004SPurna Chandra Mandal if (priv->rx_end - priv->len) \
136e19b9004SPurna Chandra Mandal *(__type *)(priv->rx) = val; \
137e19b9004SPurna Chandra Mandal priv->rx += sizeof(__type); \
138e19b9004SPurna Chandra Mandal } \
139e19b9004SPurna Chandra Mandal } \
140e19b9004SPurna Chandra Mandal \
141e19b9004SPurna Chandra Mandal static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
142e19b9004SPurna Chandra Mandal { \
143e19b9004SPurna Chandra Mandal __type val; \
144e19b9004SPurna Chandra Mandal u32 mx = pic32_tx_max(priv, sizeof(__type)); \
145e19b9004SPurna Chandra Mandal \
146e19b9004SPurna Chandra Mandal for (; mx ; mx--) { \
147e19b9004SPurna Chandra Mandal val = (__type) ~0U; \
148e19b9004SPurna Chandra Mandal if (priv->tx_end - priv->len) \
149e19b9004SPurna Chandra Mandal val = *(__type *)(priv->tx); \
150e19b9004SPurna Chandra Mandal write##__bwl(val, &priv->regs->buf.raw); \
151e19b9004SPurna Chandra Mandal priv->tx += sizeof(__type); \
152e19b9004SPurna Chandra Mandal } \
153e19b9004SPurna Chandra Mandal }
154e19b9004SPurna Chandra Mandal BUILD_SPI_FIFO_RW(byte, u8, b);
155e19b9004SPurna Chandra Mandal BUILD_SPI_FIFO_RW(word, u16, w);
156e19b9004SPurna Chandra Mandal BUILD_SPI_FIFO_RW(dword, u32, l);
157e19b9004SPurna Chandra Mandal
pic32_spi_set_word_size(struct pic32_spi_priv * priv,unsigned int wordlen)158e19b9004SPurna Chandra Mandal static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
159e19b9004SPurna Chandra Mandal unsigned int wordlen)
160e19b9004SPurna Chandra Mandal {
161e19b9004SPurna Chandra Mandal u32 bits_per_word;
162e19b9004SPurna Chandra Mandal u32 val;
163e19b9004SPurna Chandra Mandal
164e19b9004SPurna Chandra Mandal switch (wordlen) {
165e19b9004SPurna Chandra Mandal case 8:
166e19b9004SPurna Chandra Mandal priv->rx_fifo = pic32_spi_rx_byte;
167e19b9004SPurna Chandra Mandal priv->tx_fifo = pic32_spi_tx_byte;
168e19b9004SPurna Chandra Mandal bits_per_word = PIC32_SPI_CTRL_BPW_8;
169e19b9004SPurna Chandra Mandal break;
170e19b9004SPurna Chandra Mandal case 16:
171e19b9004SPurna Chandra Mandal priv->rx_fifo = pic32_spi_rx_word;
172e19b9004SPurna Chandra Mandal priv->tx_fifo = pic32_spi_tx_word;
173e19b9004SPurna Chandra Mandal bits_per_word = PIC32_SPI_CTRL_BPW_16;
174e19b9004SPurna Chandra Mandal break;
175e19b9004SPurna Chandra Mandal case 32:
176e19b9004SPurna Chandra Mandal priv->rx_fifo = pic32_spi_rx_dword;
177e19b9004SPurna Chandra Mandal priv->tx_fifo = pic32_spi_tx_dword;
178e19b9004SPurna Chandra Mandal bits_per_word = PIC32_SPI_CTRL_BPW_32;
179e19b9004SPurna Chandra Mandal break;
180e19b9004SPurna Chandra Mandal default:
181e19b9004SPurna Chandra Mandal printf("pic32-spi: unsupported wordlen\n");
182e19b9004SPurna Chandra Mandal return -EINVAL;
183e19b9004SPurna Chandra Mandal }
184e19b9004SPurna Chandra Mandal
185e19b9004SPurna Chandra Mandal /* set bits-per-word */
186e19b9004SPurna Chandra Mandal val = readl(&priv->regs->ctrl.raw);
187e19b9004SPurna Chandra Mandal val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
188e19b9004SPurna Chandra Mandal val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
189e19b9004SPurna Chandra Mandal writel(val, &priv->regs->ctrl.raw);
190e19b9004SPurna Chandra Mandal
191e19b9004SPurna Chandra Mandal /* calculate maximum number of words fifo can hold */
192e19b9004SPurna Chandra Mandal priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
193e19b9004SPurna Chandra Mandal
194e19b9004SPurna Chandra Mandal return 0;
195e19b9004SPurna Chandra Mandal }
196e19b9004SPurna Chandra Mandal
pic32_spi_claim_bus(struct udevice * slave)197e19b9004SPurna Chandra Mandal static int pic32_spi_claim_bus(struct udevice *slave)
198e19b9004SPurna Chandra Mandal {
199e19b9004SPurna Chandra Mandal struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
200e19b9004SPurna Chandra Mandal
201e19b9004SPurna Chandra Mandal /* enable chip */
202e19b9004SPurna Chandra Mandal pic32_spi_enable(priv);
203e19b9004SPurna Chandra Mandal
204e19b9004SPurna Chandra Mandal return 0;
205e19b9004SPurna Chandra Mandal }
206e19b9004SPurna Chandra Mandal
pic32_spi_release_bus(struct udevice * slave)207e19b9004SPurna Chandra Mandal static int pic32_spi_release_bus(struct udevice *slave)
208e19b9004SPurna Chandra Mandal {
209e19b9004SPurna Chandra Mandal struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
210e19b9004SPurna Chandra Mandal
211e19b9004SPurna Chandra Mandal /* disable chip */
212e19b9004SPurna Chandra Mandal pic32_spi_disable(priv);
213e19b9004SPurna Chandra Mandal
214e19b9004SPurna Chandra Mandal return 0;
215e19b9004SPurna Chandra Mandal }
216e19b9004SPurna Chandra Mandal
spi_cs_activate(struct pic32_spi_priv * priv)217e19b9004SPurna Chandra Mandal static void spi_cs_activate(struct pic32_spi_priv *priv)
218e19b9004SPurna Chandra Mandal {
219e19b9004SPurna Chandra Mandal if (!dm_gpio_is_valid(&priv->cs_gpio))
220e19b9004SPurna Chandra Mandal return;
221e19b9004SPurna Chandra Mandal
222e19b9004SPurna Chandra Mandal dm_gpio_set_value(&priv->cs_gpio, 1);
223e19b9004SPurna Chandra Mandal }
224e19b9004SPurna Chandra Mandal
spi_cs_deactivate(struct pic32_spi_priv * priv)225e19b9004SPurna Chandra Mandal static void spi_cs_deactivate(struct pic32_spi_priv *priv)
226e19b9004SPurna Chandra Mandal {
227e19b9004SPurna Chandra Mandal if (!dm_gpio_is_valid(&priv->cs_gpio))
228e19b9004SPurna Chandra Mandal return;
229e19b9004SPurna Chandra Mandal
230e19b9004SPurna Chandra Mandal dm_gpio_set_value(&priv->cs_gpio, 0);
231e19b9004SPurna Chandra Mandal }
232e19b9004SPurna Chandra Mandal
pic32_spi_xfer(struct udevice * slave,unsigned int bitlen,const void * tx_buf,void * rx_buf,unsigned long flags)233e19b9004SPurna Chandra Mandal static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
234e19b9004SPurna Chandra Mandal const void *tx_buf, void *rx_buf,
235e19b9004SPurna Chandra Mandal unsigned long flags)
236e19b9004SPurna Chandra Mandal {
237e19b9004SPurna Chandra Mandal struct dm_spi_slave_platdata *slave_plat;
238e19b9004SPurna Chandra Mandal struct udevice *bus = slave->parent;
239e19b9004SPurna Chandra Mandal struct pic32_spi_priv *priv;
240e19b9004SPurna Chandra Mandal int len = bitlen / 8;
241e19b9004SPurna Chandra Mandal int ret = 0;
242e19b9004SPurna Chandra Mandal ulong tbase;
243e19b9004SPurna Chandra Mandal
244e19b9004SPurna Chandra Mandal priv = dev_get_priv(bus);
245e19b9004SPurna Chandra Mandal slave_plat = dev_get_parent_platdata(slave);
246e19b9004SPurna Chandra Mandal
247e19b9004SPurna Chandra Mandal debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
248e19b9004SPurna Chandra Mandal bus->seq, slave_plat->cs, flags);
249e19b9004SPurna Chandra Mandal debug("msg tx %p, rx %p submitted of %d byte(s)\n",
250e19b9004SPurna Chandra Mandal tx_buf, rx_buf, len);
251e19b9004SPurna Chandra Mandal
252e19b9004SPurna Chandra Mandal /* assert cs */
253e19b9004SPurna Chandra Mandal if (flags & SPI_XFER_BEGIN)
254e19b9004SPurna Chandra Mandal spi_cs_activate(priv);
255e19b9004SPurna Chandra Mandal
256e19b9004SPurna Chandra Mandal /* set current transfer information */
257e19b9004SPurna Chandra Mandal priv->tx = tx_buf;
258e19b9004SPurna Chandra Mandal priv->rx = rx_buf;
259e19b9004SPurna Chandra Mandal priv->tx_end = priv->tx + len;
260e19b9004SPurna Chandra Mandal priv->rx_end = priv->rx + len;
261e19b9004SPurna Chandra Mandal priv->len = len;
262e19b9004SPurna Chandra Mandal
263e19b9004SPurna Chandra Mandal /* transact by polling */
264e19b9004SPurna Chandra Mandal tbase = get_timer(0);
265e19b9004SPurna Chandra Mandal for (;;) {
266e19b9004SPurna Chandra Mandal priv->tx_fifo(priv);
267e19b9004SPurna Chandra Mandal priv->rx_fifo(priv);
268e19b9004SPurna Chandra Mandal
269e19b9004SPurna Chandra Mandal /* received sufficient data */
270e19b9004SPurna Chandra Mandal if (priv->rx >= priv->rx_end) {
271e19b9004SPurna Chandra Mandal ret = 0;
272e19b9004SPurna Chandra Mandal break;
273e19b9004SPurna Chandra Mandal }
274e19b9004SPurna Chandra Mandal
275e19b9004SPurna Chandra Mandal if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
276e19b9004SPurna Chandra Mandal printf("pic32_spi: error, xfer timedout.\n");
277e19b9004SPurna Chandra Mandal flags |= SPI_XFER_END;
278e19b9004SPurna Chandra Mandal ret = -ETIMEDOUT;
279e19b9004SPurna Chandra Mandal break;
280e19b9004SPurna Chandra Mandal }
281e19b9004SPurna Chandra Mandal }
282e19b9004SPurna Chandra Mandal
283e19b9004SPurna Chandra Mandal /* deassert cs */
284e19b9004SPurna Chandra Mandal if (flags & SPI_XFER_END)
285e19b9004SPurna Chandra Mandal spi_cs_deactivate(priv);
286e19b9004SPurna Chandra Mandal
287e19b9004SPurna Chandra Mandal return ret;
288e19b9004SPurna Chandra Mandal }
289e19b9004SPurna Chandra Mandal
pic32_spi_set_speed(struct udevice * bus,uint speed)290e19b9004SPurna Chandra Mandal static int pic32_spi_set_speed(struct udevice *bus, uint speed)
291e19b9004SPurna Chandra Mandal {
292e19b9004SPurna Chandra Mandal struct pic32_spi_priv *priv = dev_get_priv(bus);
293e19b9004SPurna Chandra Mandal u32 div;
294e19b9004SPurna Chandra Mandal
295e19b9004SPurna Chandra Mandal debug("%s: %s, speed %u\n", __func__, bus->name, speed);
296e19b9004SPurna Chandra Mandal
297e19b9004SPurna Chandra Mandal /* div = [clk_in / (2 * spi_clk)] - 1 */
298e19b9004SPurna Chandra Mandal div = (priv->clk_rate / 2 / speed) - 1;
299e19b9004SPurna Chandra Mandal div &= PIC32_SPI_BAUD_MASK;
300e19b9004SPurna Chandra Mandal writel(div, &priv->regs->baud.raw);
301e19b9004SPurna Chandra Mandal
302e19b9004SPurna Chandra Mandal priv->speed_hz = speed;
303e19b9004SPurna Chandra Mandal
304e19b9004SPurna Chandra Mandal return 0;
305e19b9004SPurna Chandra Mandal }
306e19b9004SPurna Chandra Mandal
pic32_spi_set_mode(struct udevice * bus,uint mode)307e19b9004SPurna Chandra Mandal static int pic32_spi_set_mode(struct udevice *bus, uint mode)
308e19b9004SPurna Chandra Mandal {
309e19b9004SPurna Chandra Mandal struct pic32_spi_priv *priv = dev_get_priv(bus);
310e19b9004SPurna Chandra Mandal u32 val;
311e19b9004SPurna Chandra Mandal
312e19b9004SPurna Chandra Mandal debug("%s: %s, mode %d\n", __func__, bus->name, mode);
313e19b9004SPurna Chandra Mandal
314e19b9004SPurna Chandra Mandal /* set spi-clk mode */
315e19b9004SPurna Chandra Mandal val = readl(&priv->regs->ctrl.raw);
316e19b9004SPurna Chandra Mandal /* HIGH when idle */
317e19b9004SPurna Chandra Mandal if (mode & SPI_CPOL)
318e19b9004SPurna Chandra Mandal val |= PIC32_SPI_CTRL_CKP;
319e19b9004SPurna Chandra Mandal else
320e19b9004SPurna Chandra Mandal val &= ~PIC32_SPI_CTRL_CKP;
321e19b9004SPurna Chandra Mandal
322e19b9004SPurna Chandra Mandal /* TX at idle-to-active clk transition */
323e19b9004SPurna Chandra Mandal if (mode & SPI_CPHA)
324e19b9004SPurna Chandra Mandal val &= ~PIC32_SPI_CTRL_CKE;
325e19b9004SPurna Chandra Mandal else
326e19b9004SPurna Chandra Mandal val |= PIC32_SPI_CTRL_CKE;
327e19b9004SPurna Chandra Mandal
328e19b9004SPurna Chandra Mandal /* RX at end of tx */
329e19b9004SPurna Chandra Mandal val |= PIC32_SPI_CTRL_SMP;
330e19b9004SPurna Chandra Mandal writel(val, &priv->regs->ctrl.raw);
331e19b9004SPurna Chandra Mandal
332e19b9004SPurna Chandra Mandal priv->mode = mode;
333e19b9004SPurna Chandra Mandal
334e19b9004SPurna Chandra Mandal return 0;
335e19b9004SPurna Chandra Mandal }
336e19b9004SPurna Chandra Mandal
pic32_spi_set_wordlen(struct udevice * slave,unsigned int wordlen)337e19b9004SPurna Chandra Mandal static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
338e19b9004SPurna Chandra Mandal {
339e19b9004SPurna Chandra Mandal struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
340e19b9004SPurna Chandra Mandal
341e19b9004SPurna Chandra Mandal return pic32_spi_set_word_size(priv, wordlen);
342e19b9004SPurna Chandra Mandal }
343e19b9004SPurna Chandra Mandal
pic32_spi_hw_init(struct pic32_spi_priv * priv)344e19b9004SPurna Chandra Mandal static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
345e19b9004SPurna Chandra Mandal {
346e19b9004SPurna Chandra Mandal u32 val;
347e19b9004SPurna Chandra Mandal
348e19b9004SPurna Chandra Mandal /* disable module */
349e19b9004SPurna Chandra Mandal pic32_spi_disable(priv);
350e19b9004SPurna Chandra Mandal
351e19b9004SPurna Chandra Mandal val = readl(&priv->regs->ctrl);
352e19b9004SPurna Chandra Mandal
353e19b9004SPurna Chandra Mandal /* enable enhanced fifo of 128bit deep */
354e19b9004SPurna Chandra Mandal val |= PIC32_SPI_CTRL_ENHBUF;
355e19b9004SPurna Chandra Mandal priv->fifo_depth = 16;
356e19b9004SPurna Chandra Mandal
357e19b9004SPurna Chandra Mandal /* disable framing mode */
358e19b9004SPurna Chandra Mandal val &= ~PIC32_SPI_CTRL_FRMEN;
359e19b9004SPurna Chandra Mandal
360e19b9004SPurna Chandra Mandal /* enable master mode */
361e19b9004SPurna Chandra Mandal val |= PIC32_SPI_CTRL_MSTEN;
362e19b9004SPurna Chandra Mandal
363e19b9004SPurna Chandra Mandal /* select clk source */
364e19b9004SPurna Chandra Mandal val &= ~PIC32_SPI_CTRL_MCLKSEL;
365e19b9004SPurna Chandra Mandal
366e19b9004SPurna Chandra Mandal /* set manual /CS mode */
367e19b9004SPurna Chandra Mandal val &= ~PIC32_SPI_CTRL_MSSEN;
368e19b9004SPurna Chandra Mandal
369e19b9004SPurna Chandra Mandal writel(val, &priv->regs->ctrl);
370e19b9004SPurna Chandra Mandal
371e19b9004SPurna Chandra Mandal /* clear rx overflow indicator */
372e19b9004SPurna Chandra Mandal writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
373e19b9004SPurna Chandra Mandal }
374e19b9004SPurna Chandra Mandal
pic32_spi_probe(struct udevice * bus)375e19b9004SPurna Chandra Mandal static int pic32_spi_probe(struct udevice *bus)
376e19b9004SPurna Chandra Mandal {
377e19b9004SPurna Chandra Mandal struct pic32_spi_priv *priv = dev_get_priv(bus);
378e19b9004SPurna Chandra Mandal struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
379e160f7d4SSimon Glass int node = dev_of_offset(bus);
380e19b9004SPurna Chandra Mandal struct udevice *clkdev;
381e19b9004SPurna Chandra Mandal fdt_addr_t addr;
382e19b9004SPurna Chandra Mandal fdt_size_t size;
383e19b9004SPurna Chandra Mandal int ret;
384e19b9004SPurna Chandra Mandal
385e19b9004SPurna Chandra Mandal debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
386e160f7d4SSimon Glass addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
387e19b9004SPurna Chandra Mandal if (addr == FDT_ADDR_T_NONE)
388e19b9004SPurna Chandra Mandal return -EINVAL;
389e19b9004SPurna Chandra Mandal
390e19b9004SPurna Chandra Mandal priv->regs = ioremap(addr, size);
391e19b9004SPurna Chandra Mandal if (!priv->regs)
392e19b9004SPurna Chandra Mandal return -EINVAL;
393e19b9004SPurna Chandra Mandal
394e160f7d4SSimon Glass dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
395e160f7d4SSimon Glass 250000000);
396e19b9004SPurna Chandra Mandal /* get clock rate */
397e19b9004SPurna Chandra Mandal ret = clk_get_by_index(bus, 0, &clkdev);
398e19b9004SPurna Chandra Mandal if (ret < 0) {
399e19b9004SPurna Chandra Mandal printf("pic32-spi: error, clk not found\n");
400e19b9004SPurna Chandra Mandal return ret;
401e19b9004SPurna Chandra Mandal }
402e19b9004SPurna Chandra Mandal priv->clk_rate = clk_get_periph_rate(clkdev, ret);
403e19b9004SPurna Chandra Mandal
404e19b9004SPurna Chandra Mandal /* initialize HW */
405e19b9004SPurna Chandra Mandal pic32_spi_hw_init(priv);
406e19b9004SPurna Chandra Mandal
407e19b9004SPurna Chandra Mandal /* set word len */
408e19b9004SPurna Chandra Mandal pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
409e19b9004SPurna Chandra Mandal
410e19b9004SPurna Chandra Mandal /* PIC32 SPI controller can automatically drive /CS during transfer
411e19b9004SPurna Chandra Mandal * depending on fifo fill-level. /CS will stay asserted as long as
412e19b9004SPurna Chandra Mandal * TX fifo is non-empty, else will be deasserted confirming completion
413e19b9004SPurna Chandra Mandal * of the ongoing transfer. To avoid this sort of error we will drive
414e19b9004SPurna Chandra Mandal * /CS manually by toggling cs-gpio pins.
415e19b9004SPurna Chandra Mandal */
416150c5afeSSimon Glass ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
417e19b9004SPurna Chandra Mandal &priv->cs_gpio, GPIOD_IS_OUT);
418e19b9004SPurna Chandra Mandal if (ret) {
419e19b9004SPurna Chandra Mandal printf("pic32-spi: error, cs-gpios not found\n");
420e19b9004SPurna Chandra Mandal return ret;
421e19b9004SPurna Chandra Mandal }
422e19b9004SPurna Chandra Mandal
423e19b9004SPurna Chandra Mandal return 0;
424e19b9004SPurna Chandra Mandal }
425e19b9004SPurna Chandra Mandal
426e19b9004SPurna Chandra Mandal static const struct dm_spi_ops pic32_spi_ops = {
427e19b9004SPurna Chandra Mandal .claim_bus = pic32_spi_claim_bus,
428e19b9004SPurna Chandra Mandal .release_bus = pic32_spi_release_bus,
429e19b9004SPurna Chandra Mandal .xfer = pic32_spi_xfer,
430e19b9004SPurna Chandra Mandal .set_speed = pic32_spi_set_speed,
431e19b9004SPurna Chandra Mandal .set_mode = pic32_spi_set_mode,
432e19b9004SPurna Chandra Mandal .set_wordlen = pic32_spi_set_wordlen,
433e19b9004SPurna Chandra Mandal };
434e19b9004SPurna Chandra Mandal
435e19b9004SPurna Chandra Mandal static const struct udevice_id pic32_spi_ids[] = {
436e19b9004SPurna Chandra Mandal { .compatible = "microchip,pic32mzda-spi" },
437e19b9004SPurna Chandra Mandal { }
438e19b9004SPurna Chandra Mandal };
439e19b9004SPurna Chandra Mandal
440e19b9004SPurna Chandra Mandal U_BOOT_DRIVER(pic32_spi) = {
441e19b9004SPurna Chandra Mandal .name = "pic32_spi",
442e19b9004SPurna Chandra Mandal .id = UCLASS_SPI,
443e19b9004SPurna Chandra Mandal .of_match = pic32_spi_ids,
444e19b9004SPurna Chandra Mandal .ops = &pic32_spi_ops,
445e19b9004SPurna Chandra Mandal .priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
446e19b9004SPurna Chandra Mandal .probe = pic32_spi_probe,
447e19b9004SPurna Chandra Mandal };
448