phytec/pcm058/pcm058.c

1 // SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/mx6-ddr.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/mach-imx/spi.h>
70 	gd->ram_size = imx_ddr_size();  in dram_init()
183 	return devno - 1;  in board_mmc_get_env_dev()
188 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;  in board_mmc_getcd()
191 	switch (cfg->esdhc_base) {  in board_mmc_getcd()
228 			return -EINVAL;  in board_mmc_init()
238 	struct src *psrc = (struct src *)SRC_BASE_ADDR;  in board_mmc_init()
239 	unsigned reg = readl(&psrc->sbmr1) >> 11;  in board_mmc_init()
257 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;  in board_mmc_init()
297 	/* gate ENFC_CLK_ROOT clock first,before clk source switch */  in setup_gpmi_nand()
298 	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);  in setup_gpmi_nand()
301 	clrsetbits_le32(&mxc_ccm->cs2cdr,  in setup_gpmi_nand()
310 	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);  in setup_gpmi_nand()
313 	setbits_le32(&mxc_ccm->CCGR4,  in setup_gpmi_nand()
321 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);  in setup_gpmi_nand()
328 		return -EINVAL;  in board_spi_cs_gpio()
350 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;  in board_init()
370  * see Table 8-11 and Table 5-9
372  *  BOOT_CFG1[5] = 0 - raw NAND
373  *  BOOT_CFG1[4] = 0 - default pad settings
374  *  BOOT_CFG1[3:2] = 00 - devices = 1
375  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
376  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
377  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
378  *  BOOT_CFG2[0] = 0 - Reset time 12ms
480 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
481 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
482 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
483 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
484 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
485 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
486 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
556 	/* UART clocks enabled and gd valid - init serial console */  in board_init_f()
563 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()