Lines Matching +full:spi +full:- +full:src +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
6 * Leo Sartre, <lsartre@adeneo-embedded.com>
12 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/sata.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/mxc_i2c.h>
36 #include <spi.h>
64 gd->ram_size = imx_ddr_size(); in dram_init()
224 return -EINVAL; in power_init_board()
271 bus = fec_get_miibus(IMX_FEC_BASE, -1); in board_eth_init()
273 return -EINVAL; in board_eth_init()
277 ret = -ENODEV; in board_eth_init()
286 /* re-configure for Micrel KSZ9031 */ in board_eth_init()
288 phydev->addr); in board_eth_init()
290 /* phy reset: gpio3-23 */ in board_eth_init()
292 gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2)); in board_eth_init()
303 /* configure Atheros AR8035 - actually nothing to do */ in board_eth_init()
305 phydev->addr); in board_eth_init()
307 printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2); in board_eth_init()
308 ret = -EINVAL; in board_eth_init()
312 ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); in board_eth_init()
368 /* enable AR8035 ouput a 125MHz clk from CLK_25M */ in mx6_rgmii_rework()
395 if (phydev->drv->config) in board_phy_config()
396 phydev->drv->config(phydev); in board_phy_config()
423 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; in board_mmc_getcd()
426 switch (cfg->esdhc_base) { in board_mmc_getcd()
470 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
493 return -EINVAL; in board_ehci_hcd_init()
509 return -EINVAL; in board_ehci_power()
528 clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK | in disable_lvds()
540 .bus = -1,
547 "Hannstar-XGA",
561 .bus = -1,
590 if (dev->detect && dev->detect(dev)) { in board_video_skip()
591 panel = dev->mode.name; in board_video_skip()
592 printf("auto-detected panel %s\n", panel); in board_video_skip()
620 return -EINVAL; in board_video_skip()
636 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK | in setup_display()
639 /* set LDB0, LDB1 clk select to 011/011 */ in setup_display()
640 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
645 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
647 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | in setup_display()
650 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
664 writel(reg, &iomux->gpr[2]); in setup_display()
666 reg = readl(&iomux->gpr[3]); in setup_display()
671 writel(reg, &iomux->gpr[3]); in setup_display()
676 * Use always serial for U-Boot console
695 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; in board_init()
721 type = "Dual-Lite"; in checkboard()
725 printf("Board: conga-QMX6 %s\n", type); in checkboard()
733 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL; in board_spi_cs_gpio()
767 #include <asm/arch/mx6-ddr.h>
771 #include <spi.h>
949 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
950 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
951 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
952 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
953 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
954 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
955 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
971 static void conv_ascii(unsigned char *dst, unsigned char *src, int len) in conv_ascii() argument
974 unsigned char *sptr = src; in conv_ascii()
983 remain--; in conv_ascii()
988 #define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
991 struct spi_flash *spi; in is_2gb() local
997 spi = spi_flash_probe(CONFIG_ENV_SPI_BUS, in is_2gb()
1000 ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata), in is_2gb()
1006 conv_ascii(outbuf, data->pn, sizeof(data->pn)); in is_2gb()
1069 /* UART clocks enabled and gd valid - init serial console */ in board_init_f()
1082 memset(__bss_start, 0, __bss_end - __bss_start); in board_init_f()