Lines Matching +full:spi +full:- +full:src +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
21 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
28 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
53 * Put peripheral and main pll src to reset value to avoid glitch.
82 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
83 &clock_manager_base->per_pll.en); in cm_basic_init()
92 &clock_manager_base->main_pll.en); in cm_basic_init()
94 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
97 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
106 &clock_manager_base->main_pll.vco); in cm_basic_init()
109 &clock_manager_base->per_pll.vco); in cm_basic_init()
112 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
122 &clock_manager_base->per_pll.src); in cm_basic_init()
124 &clock_manager_base->main_pll.l4src); in cm_basic_init()
127 readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
128 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
129 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
136 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); in cm_basic_init()
137 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
138 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
147 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()
150 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); in cm_basic_init()
153 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); in cm_basic_init()
156 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); in cm_basic_init()
159 writel(cfg->cfg2fuser0clk, in cm_basic_init()
160 &clock_manager_base->main_pll.cfgs2fuser0clk); in cm_basic_init()
163 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); in cm_basic_init()
166 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); in cm_basic_init()
169 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); in cm_basic_init()
171 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); in cm_basic_init()
174 writel(cfg->mainnandsdmmcclk, in cm_basic_init()
175 &clock_manager_base->main_pll.mainnandsdmmcclk); in cm_basic_init()
177 writel(cfg->pernandsdmmcclk, in cm_basic_init()
178 &clock_manager_base->per_pll.pernandsdmmcclk); in cm_basic_init()
181 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); in cm_basic_init()
184 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); in cm_basic_init()
192 writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, in cm_basic_init()
193 &clock_manager_base->main_pll.vco); in cm_basic_init()
196 writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, in cm_basic_init()
197 &clock_manager_base->per_pll.vco); in cm_basic_init()
200 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, in cm_basic_init()
201 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
204 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); in cm_basic_init()
206 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); in cm_basic_init()
208 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); in cm_basic_init()
211 writel(cfg->perdiv, &clock_manager_base->per_pll.div); in cm_basic_init()
213 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); in cm_basic_init()
218 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, in cm_basic_init()
219 &clock_manager_base->sdr_pll.ddrdqsclk); in cm_basic_init()
221 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, in cm_basic_init()
222 &clock_manager_base->sdr_pll.ddr2xdqsclk); in cm_basic_init()
224 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, in cm_basic_init()
225 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
227 writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, in cm_basic_init()
228 &clock_manager_base->sdr_pll.s2fuser2clk); in cm_basic_init()
234 u32 mainvco = readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
238 &clock_manager_base->main_pll.vco); in cm_basic_init()
240 u32 periphvco = readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
244 &clock_manager_base->per_pll.vco); in cm_basic_init()
247 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| in cm_basic_init()
249 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
253 &clock_manager_base->main_pll.vco); in cm_basic_init()
257 &clock_manager_base->per_pll.vco); in cm_basic_init()
260 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, in cm_basic_init()
261 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
267 ret = cm_write_with_phase(cfg->ddrdqsclk, in cm_basic_init()
268 &clock_manager_base->sdr_pll.ddrdqsclk, in cm_basic_init()
274 ret = cm_write_with_phase(cfg->ddr2xdqsclk, in cm_basic_init()
275 &clock_manager_base->sdr_pll.ddr2xdqsclk, in cm_basic_init()
280 ret = cm_write_with_phase(cfg->ddrdqclk, in cm_basic_init()
281 &clock_manager_base->sdr_pll.ddrdqclk, in cm_basic_init()
286 ret = cm_write_with_phase(cfg->s2fuser2clk, in cm_basic_init()
287 &clock_manager_base->sdr_pll.s2fuser2clk, in cm_basic_init()
296 cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); in cm_basic_init()
302 writel(cfg->persrc, &clock_manager_base->per_pll.src); in cm_basic_init()
303 writel(cfg->l4src, &clock_manager_base->main_pll.l4src); in cm_basic_init()
305 /* Now ungate non-hw-managed clocks */ in cm_basic_init()
306 writel(~0, &clock_manager_base->main_pll.en); in cm_basic_init()
307 writel(~0, &clock_manager_base->per_pll.en); in cm_basic_init()
308 writel(~0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
313 &clock_manager_base->inter); in cm_basic_init()
323 reg = readl(&clock_manager_base->main_pll.vco); in cm_get_main_vco_clk_hz()
338 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
349 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
365 reg = readl(&clock_manager_base->altera.mpuclk); in cm_get_mpu_clk_hz()
367 reg = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz()
377 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
388 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
395 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); in cm_get_sdram_clk_hz()
408 reg = readl(&clock_manager_base->main_pll.l4src); in cm_get_l4_sp_clk_hz()
415 /* get the clock prior L4 SP divider (main clk) */ in cm_get_l4_sp_clk_hz()
416 reg = readl(&clock_manager_base->altera.mainclk); in cm_get_l4_sp_clk_hz()
418 reg = readl(&clock_manager_base->main_pll.mainclk); in cm_get_l4_sp_clk_hz()
424 reg = readl(&clock_manager_base->per_pll.perbaseclk); in cm_get_l4_sp_clk_hz()
429 reg = readl(&clock_manager_base->main_pll.maindiv); in cm_get_l4_sp_clk_hz()
442 reg = readl(&clock_manager_base->per_pll.src); in cm_get_mmc_controller_clk_hz()
452 reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); in cm_get_mmc_controller_clk_hz()
458 reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); in cm_get_mmc_controller_clk_hz()
472 reg = readl(&clock_manager_base->per_pll.src); in cm_get_qspi_controller_clk_hz()
482 reg = readl(&clock_manager_base->main_pll.mainqspiclk); in cm_get_qspi_controller_clk_hz()
488 reg = readl(&clock_manager_base->per_pll.perqspiclk); in cm_get_qspi_controller_clk_hz()
502 reg = readl(&clock_manager_base->per_pll.perbaseclk); in cm_get_spi_controller_clk_hz()
527 printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); in cm_print_clock_quick_summary()