Home
last modified time | relevance | path

Searched +full:smp +full:- +full:sram (Results 1 – 25 of 89) sorted by relevance

1234

/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
/openbmc/linux/arch/arm/mach-shmobile/
H A Dpm-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 Power management support
5 * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
14 #include <linux/smp.h>
18 #include "rcar-gen2.h"
33 #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
35 #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
37 /* On-chip RAM */
60 if (of_device_is_compatible(np, "arm,cortex-a15")) in rcar_gen2_pm_init()
62 else if (of_device_is_compatible(np, "arm,cortex-a7")) in rcar_gen2_pm_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Dmpu.txt1 * TI - MPU (Main Processor Unit) subsystem
8 - compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
11 - ti,hwmods: "mpu"
14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
18 First should be type 'protect-exec' for the driver to use to copy
20 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
25 - For an OMAP5 SMP system:
[all …]
/openbmc/linux/arch/arm/mach-rockchip/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/smp.h>
57 np = dev->of_node; in rockchip_get_core_reset()
92 ret = -1; in pmu_set_power_domain()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
146 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
160 * Starting cores execute the code residing at the start of the on-chip sram
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/mach-meson/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/smp.h>
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
66 /* SMP SRAM */ in meson_smp_prepare_cpus()
69 pr_err("Missing SRAM node\n"); in meson_smp_prepare_cpus()
76 pr_err("Couldn't map SRAM registers\n"); in meson_smp_prepare_cpus()
106 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
107 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
112 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
[all …]
/openbmc/linux/drivers/soc/renesas/
H A Dr9a06g032-smp.c1 // SPDX-License-Identifier: GPL-2.0
8 * Derived from actions,s500-smp
14 #include <linux/smp.h>
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
67 if (of_find_property(dn, "cpu-release-addr", &dns)) { in r9a06g032_smp_prepare_cpus()
72 "cpu-release-addr", &temp); in r9a06g032_smp_prepare_cpus()
[all …]
/openbmc/linux/arch/csky/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
39 select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
136 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
151 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
186 # VA_BITS - PAGE_SHIFT - 3
236 prompt "C-SKY PMU type"
266 bool "Tightly-Coupled/Sram Memory"
269 The implementation are not only used by TCM (Tightly-Coupled Memory)
270 but also used by sram on SOC bus. It follow existed linux tcm
272 re-used directly.
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
[all …]
H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
/openbmc/u-boot/arch/arm/mach-mediatek/mt7629/
H A Dlowlevel_init.S1 /* SPDX-License-Identifier: GPL-2.0 */
19 /* Return to U-Boot via saved link register */
30 /* enable SMP bit */
60 /* copy wait code into SRAM */
62 ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
64 stm r0, {r1 - r8}
70 /* jump to wait code in SRAM */
76 /* This function will be copied into SRAM */
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/mach-exynos/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
20 select HAVE_ARM_SCU if SMP
27 select SRAM
51 Samsung Exynos3 (Cortex-A7) SoC based systems
61 Samsung Exynos4 (Cortex-A9) SoC based systems
67 Samsung Exynos5 (Cortex-A15/A7) SoC based systems
110 select EXYNOS_MCPM if SMP
/openbmc/linux/arch/arm/mach-omap2/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := id.o io.o control.o devices.o fb.o pm.o \
8 common.o dma.o omap-headsmp.o sram.o
10 hwmod-common = omap_hwmod.o \
15 clock-common = clock.o
16 secure-common = omap-smc.o omap-secure.o
18 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
19 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
20 obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
21 obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 select SRAM
14 Support for Freescale MXC/iMX-based family of processors
35 def_bool y if SMP
92 comment "Cortex-A platforms"
135 select ARM_ERRATA_764369 if SMP
138 select HAVE_ARM_SCU if SMP
197 comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
/openbmc/u-boot/arch/arm/dts/
H A Drk3188.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
25 operating-points = <
[all …]
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
13 interrupt-parent = <&gic>;
32 arm-pmu {
33 compatible = "arm,cortex-a7-pmu";
36 interrupt-affinity = <&cpu0>, <&cpu1>;
[all …]
/openbmc/linux/arch/powerpc/platforms/85xx/
H A Dxes_mpc85xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * X-ES board-specific functionality
9 * Author: Nate Case <ncase@xes-inc.com>
24 #include <asm/pci-bridge.h>
31 #include "smp.h"
38 #define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
56 * xMon may have enabled part of L2 as SRAM, so we need to set it in xes_mpc85xx_configure_l2()
65 * Assume L2 SRAM is used fully for cache, so set in xes_mpc85xx_configure_l2()
81 * Legacy xMon firmware on some X-ES boards does not enable L2 in xes_mpc85xx_fixups()
84 for_each_node_by_name(np, "l2-cache-controller") { in xes_mpc85xx_fixups()
[all …]
/openbmc/linux/arch/arm/mach-spear/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/platsmp.c
5 * based upon linux/arch/arm/mach-realview/platsmp.c
14 #include <linux/smp.h>
20 /* XXX spear_pen_release is cargo culted code - DO NOT COPY XXX */
21 volatile int spear_pen_release = -1;
24 * XXX CARGO CULTED CODE - DO NOT COPY XXX
47 spear_write_pen_release(-1); in spear13xx_secondary_init()
68 * the holding pen - release it, then wait for it to flag in spear13xx_boot_secondary()
79 if (spear_pen_release == -1) in spear13xx_boot_secondary()
[all …]
/openbmc/linux/arch/arm/mach-milbeaut/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/irqchip/arm-gic.h>
28 return -ENXIO; in m10v_boot_secondary()
35 return -EINVAL; in m10v_boot_secondary()
51 np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram"); in m10v_smp_init()
97 CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops);
142 if (of_machine_is_compatible("socionext,milbeaut-evb")) in m10v_pm_init()
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
/openbmc/linux/arch/arm/mach-sunxi/
H A Dmc_smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
22 #include <linux/smp.h>
70 /* R_CPUCFG registers, specific to sun8i-a83t */
[all …]
/openbmc/qemu/docs/system/arm/
H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700
9 with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz)
16 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
17 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
18 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
19 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
23 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
24 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
[all …]

1234