1ad1d7d7cSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
23038acf9SNate Case /*
33038acf9SNate Case * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
43038acf9SNate Case *
53038acf9SNate Case * X-ES board-specific functionality
63038acf9SNate Case *
73038acf9SNate Case * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
83038acf9SNate Case *
93038acf9SNate Case * Author: Nate Case <ncase@xes-inc.com>
103038acf9SNate Case */
113038acf9SNate Case
123038acf9SNate Case #include <linux/stddef.h>
133038acf9SNate Case #include <linux/kernel.h>
143038acf9SNate Case #include <linux/pci.h>
153038acf9SNate Case #include <linux/kdev_t.h>
163038acf9SNate Case #include <linux/delay.h>
173038acf9SNate Case #include <linux/seq_file.h>
183038acf9SNate Case #include <linux/interrupt.h>
19*81d7cac4SRob Herring #include <linux/of.h>
20e6f6390aSChristophe Leroy #include <linux/of_address.h>
213038acf9SNate Case
223038acf9SNate Case #include <asm/time.h>
233038acf9SNate Case #include <asm/machdep.h>
243038acf9SNate Case #include <asm/pci-bridge.h>
253038acf9SNate Case #include <mm/mmu_decl.h>
263038acf9SNate Case #include <asm/udbg.h>
273038acf9SNate Case #include <asm/mpic.h>
283038acf9SNate Case
293038acf9SNate Case #include <sysdev/fsl_soc.h>
303038acf9SNate Case #include <sysdev/fsl_pci.h>
31582d3e09SKyle Moffett #include "smp.h"
323038acf9SNate Case
33543a07b1SDmitry Eremin-Solenikov #include "mpc85xx.h"
34543a07b1SDmitry Eremin-Solenikov
353038acf9SNate Case /* A few bit definitions needed for fixups on some boards */
363038acf9SNate Case #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
373038acf9SNate Case #define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
383038acf9SNate Case #define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
393038acf9SNate Case
xes_mpc85xx_pic_init(void)403038acf9SNate Case void __init xes_mpc85xx_pic_init(void)
413038acf9SNate Case {
42e55d7f73SKyle Moffett struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
433038acf9SNate Case 0, 256, " OpenPIC ");
443038acf9SNate Case BUG_ON(mpic == NULL);
453038acf9SNate Case mpic_init(mpic);
463038acf9SNate Case }
473038acf9SNate Case
xes_mpc85xx_configure_l2(void __iomem * l2_base)48407454caSNick Child static void __init xes_mpc85xx_configure_l2(void __iomem *l2_base)
493038acf9SNate Case {
503038acf9SNate Case volatile uint32_t ctl, tmp;
513038acf9SNate Case
523038acf9SNate Case asm volatile("msync; isync");
533038acf9SNate Case tmp = in_be32(l2_base);
543038acf9SNate Case
553038acf9SNate Case /*
563038acf9SNate Case * xMon may have enabled part of L2 as SRAM, so we need to set it
573038acf9SNate Case * up for all cache mode just to be safe.
583038acf9SNate Case */
593038acf9SNate Case printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
603038acf9SNate Case
613038acf9SNate Case ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
6271a157e8SGrant Likely if (of_machine_is_compatible("MPC8540") ||
6371a157e8SGrant Likely of_machine_is_compatible("MPC8560"))
643038acf9SNate Case /*
653038acf9SNate Case * Assume L2 SRAM is used fully for cache, so set
663038acf9SNate Case * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
673038acf9SNate Case */
683038acf9SNate Case ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
693038acf9SNate Case
703038acf9SNate Case asm volatile("msync; isync");
713038acf9SNate Case out_be32(l2_base, ctl);
723038acf9SNate Case asm volatile("msync; isync");
733038acf9SNate Case }
743038acf9SNate Case
xes_mpc85xx_fixups(void)75407454caSNick Child static void __init xes_mpc85xx_fixups(void)
763038acf9SNate Case {
773038acf9SNate Case struct device_node *np;
783038acf9SNate Case int err;
793038acf9SNate Case
803038acf9SNate Case /*
813038acf9SNate Case * Legacy xMon firmware on some X-ES boards does not enable L2
823038acf9SNate Case * as cache. We must ensure that they get enabled here.
833038acf9SNate Case */
843038acf9SNate Case for_each_node_by_name(np, "l2-cache-controller") {
853038acf9SNate Case struct resource r[2];
863038acf9SNate Case void __iomem *l2_base;
873038acf9SNate Case
883038acf9SNate Case /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
893038acf9SNate Case if (!of_device_is_compatible(np,
903038acf9SNate Case "fsl,mpc8548-l2-cache-controller") &&
913038acf9SNate Case !of_device_is_compatible(np,
923038acf9SNate Case "fsl,mpc8540-l2-cache-controller") &&
933038acf9SNate Case !of_device_is_compatible(np,
943038acf9SNate Case "fsl,mpc8560-l2-cache-controller"))
953038acf9SNate Case continue;
963038acf9SNate Case
973038acf9SNate Case err = of_address_to_resource(np, 0, &r[0]);
983038acf9SNate Case if (err) {
993038acf9SNate Case printk(KERN_WARNING "xes_mpc85xx: Could not get "
100b7c670d6SRob Herring "resource for device tree node '%pOF'",
101b7c670d6SRob Herring np);
1023038acf9SNate Case continue;
1033038acf9SNate Case }
1043038acf9SNate Case
10528f65c11SJoe Perches l2_base = ioremap(r[0].start, resource_size(&r[0]));
1063038acf9SNate Case
1073038acf9SNate Case xes_mpc85xx_configure_l2(l2_base);
1083038acf9SNate Case }
1093038acf9SNate Case }
1103038acf9SNate Case
1113038acf9SNate Case /*
1123038acf9SNate Case * Setup the architecture
1133038acf9SNate Case */
xes_mpc85xx_setup_arch(void)1143038acf9SNate Case static void __init xes_mpc85xx_setup_arch(void)
1153038acf9SNate Case {
1163038acf9SNate Case struct device_node *root;
1173038acf9SNate Case const char *model = "Unknown";
1183038acf9SNate Case
1193038acf9SNate Case root = of_find_node_by_path("/");
1203038acf9SNate Case if (root == NULL)
1213038acf9SNate Case return;
1223038acf9SNate Case
1233038acf9SNate Case model = of_get_property(root, "model", NULL);
1243038acf9SNate Case
1253038acf9SNate Case printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
1263038acf9SNate Case model + strlen("xes,"));
1273038acf9SNate Case
1283038acf9SNate Case xes_mpc85xx_fixups();
1293038acf9SNate Case
1303038acf9SNate Case mpc85xx_smp_init();
131905e75c4SJia Hongtao
132905e75c4SJia Hongtao fsl_pci_assign_primary();
1333038acf9SNate Case }
1343038acf9SNate Case
135905e75c4SJia Hongtao machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
136905e75c4SJia Hongtao machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
137905e75c4SJia Hongtao machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
1383038acf9SNate Case
define_machine(xes_mpc8572)1393038acf9SNate Case define_machine(xes_mpc8572) {
1403038acf9SNate Case .name = "X-ES MPC8572",
1411c96fcdeSChristophe Leroy .compatible = "xes,MPC8572",
1423038acf9SNate Case .setup_arch = xes_mpc85xx_setup_arch,
1433038acf9SNate Case .init_IRQ = xes_mpc85xx_pic_init,
1443038acf9SNate Case #ifdef CONFIG_PCI
1453038acf9SNate Case .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
14648b16180SWang Dongsheng .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
1473038acf9SNate Case #endif
1483038acf9SNate Case .get_irq = mpic_get_irq,
1493038acf9SNate Case .progress = udbg_progress,
1503038acf9SNate Case };
1513038acf9SNate Case
define_machine(xes_mpc8548)1523038acf9SNate Case define_machine(xes_mpc8548) {
1533038acf9SNate Case .name = "X-ES MPC8548",
1541c96fcdeSChristophe Leroy .compatible = "xes,MPC8548",
1553038acf9SNate Case .setup_arch = xes_mpc85xx_setup_arch,
1563038acf9SNate Case .init_IRQ = xes_mpc85xx_pic_init,
1573038acf9SNate Case #ifdef CONFIG_PCI
1583038acf9SNate Case .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
15948b16180SWang Dongsheng .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
1603038acf9SNate Case #endif
1613038acf9SNate Case .get_irq = mpic_get_irq,
1623038acf9SNate Case .progress = udbg_progress,
1633038acf9SNate Case };
1643038acf9SNate Case
define_machine(xes_mpc8540)1653038acf9SNate Case define_machine(xes_mpc8540) {
1663038acf9SNate Case .name = "X-ES MPC8540",
1671c96fcdeSChristophe Leroy .compatible = "xes,MPC8540",
1683038acf9SNate Case .setup_arch = xes_mpc85xx_setup_arch,
1693038acf9SNate Case .init_IRQ = xes_mpc85xx_pic_init,
1703038acf9SNate Case #ifdef CONFIG_PCI
1713038acf9SNate Case .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
17248b16180SWang Dongsheng .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
1733038acf9SNate Case #endif
1743038acf9SNate Case .get_irq = mpic_get_irq,
1753038acf9SNate Case .progress = udbg_progress,
1763038acf9SNate Case };
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