/openbmc/u-boot/drivers/power/domain/ |
H A D | sandbox-power-domain.c | 37 struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev); in sandbox_power_domain_on() local 41 sbr->on[power_domain->id] = true; in sandbox_power_domain_on() 48 struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev); in sandbox_power_domain_off() local 52 sbr->on[power_domain->id] = false; in sandbox_power_domain_off() 95 struct sandbox_power_domain *sbr = dev_get_priv(dev); in sandbox_power_domain_query() local 102 return sbr->on[id]; in sandbox_power_domain_query()
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/openbmc/u-boot/drivers/reset/ |
H A D | sandbox-reset.c | 41 struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev); in sandbox_reset_assert() local 45 sbr->signals[reset_ctl->id].asserted = true; in sandbox_reset_assert() 52 struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev); in sandbox_reset_deassert() local 56 sbr->signals[reset_ctl->id].asserted = false; in sandbox_reset_deassert() 99 struct sandbox_reset *sbr = dev_get_priv(dev); in sandbox_reset_query() local 106 return sbr->signals[id].asserted; in sandbox_reset_query()
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/openbmc/u-boot/drivers/serial/ |
H A D | serial_lpuart.c | 147 u16 sbr; in _lpuart_serial_setbrg() local 158 sbr = (u16)(clk / (16 * baudrate)); in _lpuart_serial_setbrg() 161 __raw_writeb(sbr >> 8, &base->ubdh); in _lpuart_serial_setbrg() 162 __raw_writeb(sbr & 0xff, &base->ubdl); in _lpuart_serial_setbrg() 235 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; in _lpuart32_serial_setbrg_7ulp() local 249 sbr = 0; in _lpuart32_serial_setbrg_7ulp() 261 /* select best values between sbr and sbr+1 */ in _lpuart32_serial_setbrg_7ulp() 270 sbr = tmp_sbr; in _lpuart32_serial_setbrg_7ulp() 291 tmp |= LPUART_BAUD_SBR(sbr); in _lpuart32_serial_setbrg_7ulp() 305 u32 sbr; in _lpuart32_serial_setbrg() local [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | snps,dw-umctl2-ddrc.yaml | 70 enum: [ pclk, aclk, core, sbr ] 82 enum: [ prst, arst, core, sbr ] 115 clock-names = "pclk", "aclk", "core", "sbr";
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/openbmc/linux/drivers/infiniband/hw/hfi1/ |
H A D | pcie.c | 768 * before the SBR for the Pcie Gen3. 792 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 818 * This is an end around to do an SBR during probe time. A new API needs in trigger_sbr() 1011 /* hold the SBus resource across the firmware download and SBR */ in do_pcie_gen3_transition() 1047 * will be performed automatically after the SBR when the target in do_pcie_gen3_transition() 1247 /* hold DC in reset across the SBR */ in do_pcie_gen3_transition() 1250 /* save firmware control across the SBR */ in do_pcie_gen3_transition() 1265 * step 7: initiate the secondary bus reset (SBR) in do_pcie_gen3_transition() 1280 "%s: read of VendorID failed after SBR, err %d\n", in do_pcie_gen3_transition() 1286 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); in do_pcie_gen3_transition() [all …]
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H A D | chip.h | 722 #define SBUS_TIMEOUT 4000 /* long enough for a FW download and SBR */
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/openbmc/linux/drivers/tty/serial/ |
H A D | fsl_lpuart.c | 1986 unsigned int sbr, brfa; in lpuart_set_termios() local 2104 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios() 2105 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios() 2107 bdh |= (sbr >> 8) & 0x1F; in lpuart_set_termios() 2112 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios() 2134 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; in __lpuart32_serial_setbrg() local 2144 * Baud Rate = baud clock / ((OSR+1) × SBR) in __lpuart32_serial_setbrg() 2148 sbr = 0; in __lpuart32_serial_setbrg() 2151 /* calculate the temporary sbr value */ in __lpuart32_serial_setbrg() 2158 * osr and sbr values in __lpuart32_serial_setbrg() [all …]
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/openbmc/linux/arch/mips/include/asm/ |
H A D | bmips-spaces.h | 5 /* Avoid collisions with system base register (SBR) region on BMIPS3300 */
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/openbmc/linux/arch/mips/include/asm/mach-bmips/ |
H A D | spaces.h | 13 /* Avoid collisions with system base register (SBR) region on BMIPS3300 */
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/openbmc/qemu/hw/pci-bridge/ |
H A D | cxl_downstream.c | 57 /* unmask SBR */ in cxl_dsp_dvsec_write_config() 58 qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n"); in cxl_dsp_dvsec_write_config()
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H A D | cxl_root_port.c | 227 /* unmask SBR */ in cxl_rp_dvsec_write_config() 228 qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n"); in cxl_rp_dvsec_write_config()
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H A D | cxl_upstream.c | 50 /* unmask SBR */ in cxl_usp_dvsec_write_config() 51 qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n"); in cxl_usp_dvsec_write_config()
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/openbmc/qemu/hw/scsi/ |
H A D | lsi53c895a.c | 36 "DMODE", "DIEN", "SBR", "DCNTL", "ADDER0", "ADDER1", "ADDER2", "ADDER3", 305 uint8_t sbr; member 417 s->sbr = 0; in lsi_soft_reset() 1758 case 0x3a: /* SBR */ in lsi_reg_readb() 1759 ret = s->sbr; in lsi_reg_readb() 2030 case 0x3a: /* SBR */ in lsi_reg_writeb() 2031 s->sbr = val; in lsi_reg_writeb() 2305 VMSTATE_UINT8(sbr, LSIState),
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/openbmc/linux/sound/soc/intel/atom/ |
H A D | sst-mfld-dsp.h | 337 u8 bdownsample; /*SBR downsampling 0 - disable 1 -enabled AAC+ only */ 341 u8 sbr_signalling;/*disable/enable/set automode the SBR tool.AAC+*/
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/openbmc/linux/drivers/media/i2c/ |
H A D | tc358746.c | 947 * sbr - source_bitrate in bits/s in tc358746_link_validate() 950 * image-width / csir >= (image-width - fifo-sz) / sbr in tc358746_link_validate() 951 * image-width * sbr / csir >= image-width - fifo-sz in tc358746_link_validate() 952 * fifo-sz >= image-width - image-width * sbr / csir; with n = csir/sbr in tc358746_link_validate()
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/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/ |
H A D | pch.h | 42 #define SBR (1 << 6) macro
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/openbmc/qemu/target/microblaze/ |
H A D | insns.decode | 226 sbr 110100 ..... ..... ..... 0100 000 0000 @typea
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/openbmc/u-boot/include/ |
H A D | sym53c8xx.h | 146 #define SBR 0x3a macro
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/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/ |
H A D | amdgpu_smu.h | 1297 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
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/openbmc/linux/arch/arm64/boot/dts/apple/ |
H A D | t8112-pmgr.dtsi | 15 label = "sbr";
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H A D | t8103-pmgr.dtsi | 15 label = "sbr";
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/openbmc/linux/drivers/pci/controller/dwc/ |
H A D | pcie-tegra194.c | 383 /* SBR & Surprise Link Down WAR */ in tegra_pcie_rp_irq_handler()
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/openbmc/qemu/hw/net/can/ |
H A D | xlnx-versal-canfd.c | 54 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
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/openbmc/linux/drivers/acpi/ |
H A D | scan.c | 1308 acpi_has_method(handle, "SBR") && in acpi_ibm_smbus_match()
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_device.c | 992 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). 2677 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */ in amdgpu_device_ip_late_init()
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