1 /*
2 * Emulated CXL Switch Downstream Port
3 *
4 * Copyright (c) 2022 Huawei Technologies.
5 *
6 * Based on xio3130_downstream.c
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "qemu/log.h"
13 #include "hw/pci/msi.h"
14 #include "hw/pci/pcie.h"
15 #include "hw/pci/pcie_port.h"
16 #include "hw/cxl/cxl.h"
17 #include "qapi/error.h"
18
19 typedef struct CXLDownstreamPort {
20 /*< private >*/
21 PCIESlot parent_obj;
22
23 /*< public >*/
24 CXLComponentState cxl_cstate;
25 } CXLDownstreamPort;
26
27 #define CXL_DOWNSTREAM_PORT_MSI_OFFSET 0x70
28 #define CXL_DOWNSTREAM_PORT_MSI_NR_VECTOR 1
29 #define CXL_DOWNSTREAM_PORT_EXP_OFFSET 0x90
30 #define CXL_DOWNSTREAM_PORT_AER_OFFSET 0x100
31 #define CXL_DOWNSTREAM_PORT_DVSEC_OFFSET \
32 (CXL_DOWNSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
33
latch_registers(CXLDownstreamPort * dsp)34 static void latch_registers(CXLDownstreamPort *dsp)
35 {
36 uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers;
37 uint32_t *write_msk = dsp->cxl_cstate.crb.cache_mem_regs_write_mask;
38
39 cxl_component_register_init_common(reg_state, write_msk,
40 CXL2_DOWNSTREAM_PORT);
41 }
42
43 /* TODO: Look at sharing this code across all CXL port types */
cxl_dsp_dvsec_write_config(PCIDevice * dev,uint32_t addr,uint32_t val,int len)44 static void cxl_dsp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
45 uint32_t val, int len)
46 {
47 CXLDownstreamPort *dsp = CXL_DSP(dev);
48 CXLComponentState *cxl_cstate = &dsp->cxl_cstate;
49
50 if (range_contains(&cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {
51 uint8_t *reg = &dev->config[addr];
52 addr -= cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC].lob;
53 if (addr == PORT_CONTROL_OFFSET) {
54 if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) {
55 /* unmask SBR */
56 qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n");
57 }
58 if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) {
59 /* Alt Memory & ID Space Enable */
60 qemu_log_mask(LOG_UNIMP,
61 "Alt Memory & ID space is not supported\n");
62
63 }
64 }
65 }
66 }
67
cxl_dsp_config_write(PCIDevice * d,uint32_t address,uint32_t val,int len)68 static void cxl_dsp_config_write(PCIDevice *d, uint32_t address,
69 uint32_t val, int len)
70 {
71 uint16_t slt_ctl, slt_sta;
72
73 pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
74 pci_bridge_write_config(d, address, val, len);
75 pcie_cap_flr_write_config(d, address, val, len);
76 pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
77 pcie_aer_write_config(d, address, val, len);
78
79 cxl_dsp_dvsec_write_config(d, address, val, len);
80 }
81
cxl_dsp_reset(DeviceState * qdev)82 static void cxl_dsp_reset(DeviceState *qdev)
83 {
84 PCIDevice *d = PCI_DEVICE(qdev);
85 CXLDownstreamPort *dsp = CXL_DSP(qdev);
86
87 pcie_cap_deverr_reset(d);
88 pcie_cap_slot_reset(d);
89 pcie_cap_arifwd_reset(d);
90 pci_bridge_reset(qdev);
91
92 latch_registers(dsp);
93 }
94
build_dvsecs(CXLComponentState * cxl)95 static void build_dvsecs(CXLComponentState *cxl)
96 {
97 uint8_t *dvsec;
98
99 dvsec = (uint8_t *)&(CXLDVSECPortExt){ 0 };
100 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT,
101 EXTENSIONS_PORT_DVSEC_LENGTH,
102 EXTENSIONS_PORT_DVSEC,
103 EXTENSIONS_PORT_DVSEC_REVID, dvsec);
104
105 dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
106 .cap = 0x27, /* Cache, IO, Mem, non-MLD */
107 .ctrl = 0x02, /* IO always enabled */
108 .status = 0x26, /* same */
109 .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */
110 };
111 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT,
112 PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH,
113 PCIE_FLEXBUS_PORT_DVSEC,
114 PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID, dvsec);
115
116 dvsec = (uint8_t *)&(CXLDVSECPortGPF){
117 .rsvd = 0,
118 .phase1_ctrl = 1, /* 1μs timeout */
119 .phase2_ctrl = 1, /* 1μs timeout */
120 };
121 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT,
122 GPF_PORT_DVSEC_LENGTH, GPF_PORT_DVSEC,
123 GPF_PORT_DVSEC_REVID, dvsec);
124
125 dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
126 .rsvd = 0,
127 .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
128 .reg0_base_hi = 0,
129 };
130 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT,
131 REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
132 REG_LOC_DVSEC_REVID, dvsec);
133 }
134
cxl_dsp_realize(PCIDevice * d,Error ** errp)135 static void cxl_dsp_realize(PCIDevice *d, Error **errp)
136 {
137 PCIEPort *p = PCIE_PORT(d);
138 PCIESlot *s = PCIE_SLOT(d);
139 CXLDownstreamPort *dsp = CXL_DSP(d);
140 CXLComponentState *cxl_cstate = &dsp->cxl_cstate;
141 ComponentRegisters *cregs = &cxl_cstate->crb;
142 MemoryRegion *component_bar = &cregs->component_registers;
143 int rc;
144
145 pci_bridge_initfn(d, TYPE_PCIE_BUS);
146 pcie_port_init_reg(d);
147
148 rc = msi_init(d, CXL_DOWNSTREAM_PORT_MSI_OFFSET,
149 CXL_DOWNSTREAM_PORT_MSI_NR_VECTOR,
150 true, true, errp);
151 if (rc) {
152 assert(rc == -ENOTSUP);
153 goto err_bridge;
154 }
155
156 rc = pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET,
157 PCI_EXP_TYPE_DOWNSTREAM, p->port,
158 errp);
159 if (rc < 0) {
160 goto err_msi;
161 }
162
163 pcie_cap_flr_init(d);
164 pcie_cap_deverr_init(d);
165 pcie_cap_slot_init(d, s);
166 pcie_cap_arifwd_init(d);
167
168 pcie_chassis_create(s->chassis);
169 rc = pcie_chassis_add_slot(s);
170 if (rc < 0) {
171 error_setg(errp, "Can't add chassis slot, error %d", rc);
172 goto err_pcie_cap;
173 }
174
175 rc = pcie_aer_init(d, PCI_ERR_VER, CXL_DOWNSTREAM_PORT_AER_OFFSET,
176 PCI_ERR_SIZEOF, errp);
177 if (rc < 0) {
178 goto err_chassis;
179 }
180
181 cxl_cstate->dvsec_offset = CXL_DOWNSTREAM_PORT_DVSEC_OFFSET;
182 cxl_cstate->pdev = d;
183 build_dvsecs(cxl_cstate);
184 cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_DSP);
185 pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX,
186 PCI_BASE_ADDRESS_SPACE_MEMORY |
187 PCI_BASE_ADDRESS_MEM_TYPE_64,
188 component_bar);
189
190 return;
191
192 err_chassis:
193 pcie_chassis_del_slot(s);
194 err_pcie_cap:
195 pcie_cap_exit(d);
196 err_msi:
197 msi_uninit(d);
198 err_bridge:
199 pci_bridge_exitfn(d);
200 }
201
cxl_dsp_exitfn(PCIDevice * d)202 static void cxl_dsp_exitfn(PCIDevice *d)
203 {
204 PCIESlot *s = PCIE_SLOT(d);
205
206 pcie_aer_exit(d);
207 pcie_chassis_del_slot(s);
208 pcie_cap_exit(d);
209 msi_uninit(d);
210 pci_bridge_exitfn(d);
211 }
212
cxl_dsp_instance_post_init(Object * obj)213 static void cxl_dsp_instance_post_init(Object *obj)
214 {
215 PCIESlot *s = PCIE_SLOT(obj);
216
217 if (!s->speed) {
218 s->speed = QEMU_PCI_EXP_LNK_2_5GT;
219 }
220
221 if (!s->width) {
222 s->width = QEMU_PCI_EXP_LNK_X1;
223 }
224 }
225
cxl_dsp_class_init(ObjectClass * oc,void * data)226 static void cxl_dsp_class_init(ObjectClass *oc, void *data)
227 {
228 DeviceClass *dc = DEVICE_CLASS(oc);
229 PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
230
231 k->config_write = cxl_dsp_config_write;
232 k->realize = cxl_dsp_realize;
233 k->exit = cxl_dsp_exitfn;
234 k->vendor_id = 0x19e5; /* Huawei */
235 k->device_id = 0xa129; /* Emulated CXL Switch Downstream Port */
236 k->revision = 0;
237 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
238 dc->desc = "CXL Switch Downstream Port";
239 dc->reset = cxl_dsp_reset;
240 }
241
242 static const TypeInfo cxl_dsp_info = {
243 .name = TYPE_CXL_DSP,
244 .instance_size = sizeof(CXLDownstreamPort),
245 .parent = TYPE_PCIE_SLOT,
246 .instance_post_init = cxl_dsp_instance_post_init,
247 .class_init = cxl_dsp_class_init,
248 .interfaces = (InterfaceInfo[]) {
249 { INTERFACE_PCIE_DEVICE },
250 { INTERFACE_CXL_DEVICE },
251 { }
252 },
253 };
254
cxl_dsp_register_type(void)255 static void cxl_dsp_register_type(void)
256 {
257 type_register_static(&cxl_dsp_info);
258 }
259
260 type_init(cxl_dsp_register_type);
261