| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | renesas,rz-mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32- bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max.
16 - Pulse input 3 lines
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| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-rz-mtu3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L MTU3a PWM Timer driver
8 …* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?lang…
11 * - When PWM is disabled, the output is driven to Hi-Z.
12 * - While the hardware supports both polarities, the driver (for now)
14 * - HW uses one counter and two match components to configure duty_cycle
16 * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM
18 * - MTU{1, 2} channels have a single IO, whereas all other HW channels have
20 * - Each IO is modelled as an independent PWM channel.
21 * - rz_mtu3_channel_io_map table is used to map the PWM channel to the
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| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PWM) += core.o
3 obj-$(CONFIG_PWM_SYSFS) += sysfs.o
4 obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
5 obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
6 obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
7 obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
8 obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
9 obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
10 obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
52 will be called pwm-ab8500.
64 will be called pwm-apple.
74 will be called pwm-atmel.
82 (Atmel High-end LCD Controller). This PWM output is mainly used
86 will be called pwm-atmel-hlcdc.
99 will be called pwm-atmel-tcb.
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| /openbmc/linux/drivers/mfd/ |
| H A D | rz-mtu3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L Multi-Function Timer Pulse Unit 3(MTU3a) Core driver
13 #include <linux/mfd/rz-mtu3.h>
20 #include "rz-mtu3.h"
28 /******* MTU3 registers (original offset is +0x1200) *******/
67 struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent); in rz_mtu3_shared_reg_read()
68 struct rz_mtu3_priv *priv = mtu->priv_data; in rz_mtu3_shared_reg_read()
71 return readw(priv->mmio + offset); in rz_mtu3_shared_reg_read()
73 return readb(priv->mmio + offset); in rz_mtu3_shared_reg_read()
79 struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent); in rz_mtu3_8bit_ch_read()
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| H A D | rz-mtu3.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MFD internals for Renesas RZ/G2L MTU3 Core driver
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| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
6 88pm860x-objs := 88pm860x-core.o 88pm860x-i2c.o
7 obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
8 obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
9 obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
10 obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
11 obj-$(CONFIG_MFD_SM501) += sm501.o
12 obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
13 obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o
14 obj-$(CONFIG_MFD_BD9571MWV) += bd9571mwv.o
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| /openbmc/linux/arch/arm64/boot/dts/renesas/ |
| H A D | rzg2ul-smarc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts
8 #include "rzg2ul-smarc-pinfunction.dtsi"
9 #include "rz-smarc-common.dtsi"
13 /delete-property/ pinctrl-0;
14 /delete-property/ pinctrl-names;
20 sound-dai = <&ssi1>;
26 #sound-dai-cells = <0>;
32 &mtu3 {
33 pinctrl-0 = <&mtu3_pins>;
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| H A D | rzg2l-smarc-pinfunction.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
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| H A D | rzg2lc-smarc-pinfunction.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC SMARC pincontrol parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
16 /* SW8 should be at position 2->1 */
24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
25 can1-stb-hog {
26 gpio-hog;
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| H A D | rzg2lc-smarc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC SMARC EVK parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi"
20 osc1: cec-clock {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
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| H A D | r9a07g043.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
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| H A D | rzg2l-smarc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
23 hdmi-out {
24 compatible = "hdmi-connector";
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| H A D | rzg2ul-smarc-pinfunction.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2UL SMARC pincontrol parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
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| H A D | r9a07g044.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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| H A D | r9a07g054.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/V2L SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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| /openbmc/linux/drivers/counter/ |
| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0-only
6 obj-$(CONFIG_COUNTER) += counter.o
7 counter-y := counter-core.o counter-sysfs.o counter-chrdev.o
9 obj-$(CONFIG_I8254) += i8254.o
10 obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
11 obj-$(CONFIG_INTERRUPT_CNT) += interrupt-cnt.o
12 obj-$(CONFIG_RZ_MTU3_CNT) += rz-mtu3-cnt.o
13 obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
14 obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
15 obj-$(CONFIG_TI_EQEP) += ti-eqep.o
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| H A D | rz-mtu3-cnt.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L MTU3a Counter driver
10 #include <linux/mfd/rz-mtu3.h>
40 * 0: 16-bit, 1: 32-bit
66 * struct rz_mtu3_cnt - MTU3 counter private data
68 * @clk: MTU3 module clock
72 * @mtu_16bit_max: Cache for 16-bit counters
73 * @mtu_32bit_max: Cache for 32-bit counters
102 return &priv->ch[ch_id]; in rz_mtu3_get_ch()
110 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_is_counter_invalid()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
38 encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
41 operation on the respective count value attribute. The 104-QUAD-8
58 module will be called ftm-quaddec.
69 will be called intel-qep.
79 module will be called interrupt-cnt.
91 module will be called microchip-tcb-capture.
94 tristate "Renesas RZ/G2L MTU3a counter driver"
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| /openbmc/linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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| H A D | opengrok2.0.log | 1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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| H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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| H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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