1254d3a72SBiju Das // SPDX-License-Identifier: GPL-2.0
2254d3a72SBiju Das /*
3254d3a72SBiju Das * Renesas RZ/G2L MTU3a PWM Timer driver
4254d3a72SBiju Das *
5254d3a72SBiju Das * Copyright (C) 2023 Renesas Electronics Corporation
6254d3a72SBiju Das *
7254d3a72SBiju Das * Hardware manual for this IP can be found here
8254d3a72SBiju Das * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en
9254d3a72SBiju Das *
10254d3a72SBiju Das * Limitations:
11254d3a72SBiju Das * - When PWM is disabled, the output is driven to Hi-Z.
12254d3a72SBiju Das * - While the hardware supports both polarities, the driver (for now)
13254d3a72SBiju Das * only handles normal polarity.
14254d3a72SBiju Das * - HW uses one counter and two match components to configure duty_cycle
15254d3a72SBiju Das * and period.
16254d3a72SBiju Das * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM
17254d3a72SBiju Das * operations. (The channels are MTU{0..4, 6, 7}.)
18254d3a72SBiju Das * - MTU{1, 2} channels have a single IO, whereas all other HW channels have
19254d3a72SBiju Das * 2 IOs.
20254d3a72SBiju Das * - Each IO is modelled as an independent PWM channel.
21254d3a72SBiju Das * - rz_mtu3_channel_io_map table is used to map the PWM channel to the
22254d3a72SBiju Das * corresponding HW channel as there are difference in number of IOs
23254d3a72SBiju Das * between HW channels.
24254d3a72SBiju Das */
25254d3a72SBiju Das
26254d3a72SBiju Das #include <linux/bitfield.h>
27254d3a72SBiju Das #include <linux/clk.h>
28254d3a72SBiju Das #include <linux/limits.h>
29254d3a72SBiju Das #include <linux/mfd/rz-mtu3.h>
30254d3a72SBiju Das #include <linux/module.h>
31254d3a72SBiju Das #include <linux/platform_device.h>
32254d3a72SBiju Das #include <linux/pm_runtime.h>
33254d3a72SBiju Das #include <linux/pwm.h>
34254d3a72SBiju Das #include <linux/time.h>
35254d3a72SBiju Das
36254d3a72SBiju Das #define RZ_MTU3_MAX_PWM_CHANNELS 12
37254d3a72SBiju Das #define RZ_MTU3_MAX_HW_CHANNELS 7
38254d3a72SBiju Das
39254d3a72SBiju Das /**
40254d3a72SBiju Das * struct rz_mtu3_channel_io_map - MTU3 pwm channel map
41254d3a72SBiju Das *
42254d3a72SBiju Das * @base_pwm_number: First PWM of a channel
43*bdebe27eSBiju Das * @num_channel_ios: number of IOs on the HW channel.
44254d3a72SBiju Das */
45254d3a72SBiju Das struct rz_mtu3_channel_io_map {
46254d3a72SBiju Das u8 base_pwm_number;
47254d3a72SBiju Das u8 num_channel_ios;
48254d3a72SBiju Das };
49254d3a72SBiju Das
50254d3a72SBiju Das /**
51254d3a72SBiju Das * struct rz_mtu3_pwm_channel - MTU3 pwm channel data
52254d3a72SBiju Das *
53254d3a72SBiju Das * @mtu: MTU3 channel data
54254d3a72SBiju Das * @map: MTU3 pwm channel map
55254d3a72SBiju Das */
56254d3a72SBiju Das struct rz_mtu3_pwm_channel {
57254d3a72SBiju Das struct rz_mtu3_channel *mtu;
58254d3a72SBiju Das const struct rz_mtu3_channel_io_map *map;
59254d3a72SBiju Das };
60254d3a72SBiju Das
61254d3a72SBiju Das /**
62254d3a72SBiju Das * struct rz_mtu3_pwm_chip - MTU3 pwm private data
63254d3a72SBiju Das *
64254d3a72SBiju Das * @chip: MTU3 pwm chip data
65254d3a72SBiju Das * @clk: MTU3 module clock
66254d3a72SBiju Das * @lock: Lock to prevent concurrent access for usage count
67254d3a72SBiju Das * @rate: MTU3 clock rate
68254d3a72SBiju Das * @user_count: MTU3 usage count
69254d3a72SBiju Das * @enable_count: MTU3 enable count
70254d3a72SBiju Das * @prescale: MTU3 prescale
71254d3a72SBiju Das * @channel_data: MTU3 pwm channel data
72254d3a72SBiju Das */
73254d3a72SBiju Das
74254d3a72SBiju Das struct rz_mtu3_pwm_chip {
75254d3a72SBiju Das struct pwm_chip chip;
76254d3a72SBiju Das struct clk *clk;
77254d3a72SBiju Das struct mutex lock;
78254d3a72SBiju Das unsigned long rate;
79254d3a72SBiju Das u32 user_count[RZ_MTU3_MAX_HW_CHANNELS];
80254d3a72SBiju Das u32 enable_count[RZ_MTU3_MAX_HW_CHANNELS];
81254d3a72SBiju Das u8 prescale[RZ_MTU3_MAX_HW_CHANNELS];
82254d3a72SBiju Das struct rz_mtu3_pwm_channel channel_data[RZ_MTU3_MAX_HW_CHANNELS];
83254d3a72SBiju Das };
84254d3a72SBiju Das
85254d3a72SBiju Das /*
86254d3a72SBiju Das * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1
87254d3a72SBiju Das * and MTU2 channel is 1 compared to 2 on others.
88254d3a72SBiju Das */
89254d3a72SBiju Das static const struct rz_mtu3_channel_io_map channel_map[] = {
90254d3a72SBiju Das { 0, 2 }, { 2, 1 }, { 3, 1 }, { 4, 2 }, { 6, 2 }, { 8, 2 }, { 10, 2 }
91254d3a72SBiju Das };
92254d3a72SBiju Das
to_rz_mtu3_pwm_chip(struct pwm_chip * chip)93254d3a72SBiju Das static inline struct rz_mtu3_pwm_chip *to_rz_mtu3_pwm_chip(struct pwm_chip *chip)
94254d3a72SBiju Das {
95254d3a72SBiju Das return container_of(chip, struct rz_mtu3_pwm_chip, chip);
96254d3a72SBiju Das }
97254d3a72SBiju Das
rz_mtu3_pwm_read_tgr_registers(struct rz_mtu3_pwm_channel * priv,u16 reg_pv_offset,u16 * pv_val,u16 reg_dc_offset,u16 * dc_val)98254d3a72SBiju Das static void rz_mtu3_pwm_read_tgr_registers(struct rz_mtu3_pwm_channel *priv,
99254d3a72SBiju Das u16 reg_pv_offset, u16 *pv_val,
100254d3a72SBiju Das u16 reg_dc_offset, u16 *dc_val)
101254d3a72SBiju Das {
102254d3a72SBiju Das *pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset);
103254d3a72SBiju Das *dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset);
104254d3a72SBiju Das }
105254d3a72SBiju Das
rz_mtu3_pwm_write_tgr_registers(struct rz_mtu3_pwm_channel * priv,u16 reg_pv_offset,u16 pv_val,u16 reg_dc_offset,u16 dc_val)106254d3a72SBiju Das static void rz_mtu3_pwm_write_tgr_registers(struct rz_mtu3_pwm_channel *priv,
107254d3a72SBiju Das u16 reg_pv_offset, u16 pv_val,
108254d3a72SBiju Das u16 reg_dc_offset, u16 dc_val)
109254d3a72SBiju Das {
110254d3a72SBiju Das rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val);
111254d3a72SBiju Das rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val);
112254d3a72SBiju Das }
113254d3a72SBiju Das
rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip * rz_mtu3,u64 period_cycles)114254d3a72SBiju Das static u8 rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip *rz_mtu3,
115254d3a72SBiju Das u64 period_cycles)
116254d3a72SBiju Das {
117254d3a72SBiju Das u32 prescaled_period_cycles;
118254d3a72SBiju Das u8 prescale;
119254d3a72SBiju Das
120254d3a72SBiju Das /*
121254d3a72SBiju Das * Supported prescale values are 1, 4, 16 and 64.
122254d3a72SBiju Das * TODO: Support prescale values 2, 8, 32, 256 and 1024.
123254d3a72SBiju Das */
124254d3a72SBiju Das prescaled_period_cycles = period_cycles >> 16;
125254d3a72SBiju Das if (prescaled_period_cycles >= 16)
126254d3a72SBiju Das prescale = 3;
127254d3a72SBiju Das else
128254d3a72SBiju Das prescale = (fls(prescaled_period_cycles) + 1) / 2;
129254d3a72SBiju Das
130254d3a72SBiju Das return prescale;
131254d3a72SBiju Das }
132254d3a72SBiju Das
133254d3a72SBiju Das static struct rz_mtu3_pwm_channel *
rz_mtu3_get_channel(struct rz_mtu3_pwm_chip * rz_mtu3_pwm,u32 hwpwm)134254d3a72SBiju Das rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm)
135254d3a72SBiju Das {
136254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv = rz_mtu3_pwm->channel_data;
137254d3a72SBiju Das unsigned int ch;
138254d3a72SBiju Das
139254d3a72SBiju Das for (ch = 0; ch < RZ_MTU3_MAX_HW_CHANNELS; ch++, priv++) {
140254d3a72SBiju Das if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm)
141254d3a72SBiju Das break;
142254d3a72SBiju Das }
143254d3a72SBiju Das
144254d3a72SBiju Das return priv;
145254d3a72SBiju Das }
146254d3a72SBiju Das
rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip * rz_mtu3_pwm,u32 hwpwm)147254d3a72SBiju Das static bool rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
148254d3a72SBiju Das u32 hwpwm)
149254d3a72SBiju Das {
150254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv;
151254d3a72SBiju Das bool is_channel_en;
152254d3a72SBiju Das u8 val;
153254d3a72SBiju Das
154254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm);
155254d3a72SBiju Das is_channel_en = rz_mtu3_is_enabled(priv->mtu);
156254d3a72SBiju Das if (!is_channel_en)
157254d3a72SBiju Das return false;
158254d3a72SBiju Das
159254d3a72SBiju Das if (priv->map->base_pwm_number == hwpwm)
160254d3a72SBiju Das val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH);
161254d3a72SBiju Das else
162254d3a72SBiju Das val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL);
163254d3a72SBiju Das
164254d3a72SBiju Das return val & RZ_MTU3_TIOR_IOA;
165254d3a72SBiju Das }
166254d3a72SBiju Das
rz_mtu3_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)167254d3a72SBiju Das static int rz_mtu3_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
168254d3a72SBiju Das {
169254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
170254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv;
171254d3a72SBiju Das bool is_mtu3_channel_available;
172254d3a72SBiju Das u32 ch;
173254d3a72SBiju Das
174254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
175254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data;
176254d3a72SBiju Das
177254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock);
178254d3a72SBiju Das /*
179254d3a72SBiju Das * Each channel must be requested only once, so if the channel
180254d3a72SBiju Das * serves two PWMs and the other is already requested, skip over
181254d3a72SBiju Das * rz_mtu3_request_channel()
182254d3a72SBiju Das */
183254d3a72SBiju Das if (!rz_mtu3_pwm->user_count[ch]) {
184254d3a72SBiju Das is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu);
185254d3a72SBiju Das if (!is_mtu3_channel_available) {
186254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock);
187254d3a72SBiju Das return -EBUSY;
188254d3a72SBiju Das }
189254d3a72SBiju Das }
190254d3a72SBiju Das
191254d3a72SBiju Das rz_mtu3_pwm->user_count[ch]++;
192254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock);
193254d3a72SBiju Das
194254d3a72SBiju Das return 0;
195254d3a72SBiju Das }
196254d3a72SBiju Das
rz_mtu3_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)197254d3a72SBiju Das static void rz_mtu3_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
198254d3a72SBiju Das {
199254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
200254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv;
201254d3a72SBiju Das u32 ch;
202254d3a72SBiju Das
203254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
204254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data;
205254d3a72SBiju Das
206254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock);
207254d3a72SBiju Das rz_mtu3_pwm->user_count[ch]--;
208254d3a72SBiju Das if (!rz_mtu3_pwm->user_count[ch])
209254d3a72SBiju Das rz_mtu3_release_channel(priv->mtu);
210254d3a72SBiju Das
211254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock);
212254d3a72SBiju Das }
213254d3a72SBiju Das
rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip * rz_mtu3_pwm,struct pwm_device * pwm)214254d3a72SBiju Das static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
215254d3a72SBiju Das struct pwm_device *pwm)
216254d3a72SBiju Das {
217254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv;
218254d3a72SBiju Das u32 ch;
219254d3a72SBiju Das u8 val;
220254d3a72SBiju Das int rc;
221254d3a72SBiju Das
222254d3a72SBiju Das rc = pm_runtime_resume_and_get(rz_mtu3_pwm->chip.dev);
223254d3a72SBiju Das if (rc)
224254d3a72SBiju Das return rc;
225254d3a72SBiju Das
226254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
227254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data;
228254d3a72SBiju Das val = RZ_MTU3_TIOR_OC_IOB_TOGGLE | RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH;
229254d3a72SBiju Das
230254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1);
231254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm)
232254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val);
233254d3a72SBiju Das else
234254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val);
235254d3a72SBiju Das
236254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock);
237254d3a72SBiju Das if (!rz_mtu3_pwm->enable_count[ch])
238254d3a72SBiju Das rz_mtu3_enable(priv->mtu);
239254d3a72SBiju Das
240254d3a72SBiju Das rz_mtu3_pwm->enable_count[ch]++;
241254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock);
242254d3a72SBiju Das
243254d3a72SBiju Das return 0;
244254d3a72SBiju Das }
245254d3a72SBiju Das
rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip * rz_mtu3_pwm,struct pwm_device * pwm)246254d3a72SBiju Das static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
247254d3a72SBiju Das struct pwm_device *pwm)
248254d3a72SBiju Das {
249254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv;
250254d3a72SBiju Das u32 ch;
251254d3a72SBiju Das
252254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
253254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data;
254254d3a72SBiju Das
255254d3a72SBiju Das /* Disable output pins of MTU3 channel */
256254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm)
257254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN);
258254d3a72SBiju Das else
259254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN);
260254d3a72SBiju Das
261254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock);
262254d3a72SBiju Das rz_mtu3_pwm->enable_count[ch]--;
263254d3a72SBiju Das if (!rz_mtu3_pwm->enable_count[ch])
264254d3a72SBiju Das rz_mtu3_disable(priv->mtu);
265254d3a72SBiju Das
266254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock);
267254d3a72SBiju Das
268254d3a72SBiju Das pm_runtime_put_sync(rz_mtu3_pwm->chip.dev);
269254d3a72SBiju Das }
270254d3a72SBiju Das
rz_mtu3_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)271254d3a72SBiju Das static int rz_mtu3_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
272254d3a72SBiju Das struct pwm_state *state)
273254d3a72SBiju Das {
274254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
275254d3a72SBiju Das int rc;
276254d3a72SBiju Das
277254d3a72SBiju Das rc = pm_runtime_resume_and_get(chip->dev);
278254d3a72SBiju Das if (rc)
279254d3a72SBiju Das return rc;
280254d3a72SBiju Das
281254d3a72SBiju Das state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm);
282254d3a72SBiju Das if (state->enabled) {
283254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv;
284254d3a72SBiju Das u8 prescale, val;
285254d3a72SBiju Das u16 dc, pv;
286254d3a72SBiju Das u64 tmp;
287254d3a72SBiju Das
288254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
289254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm)
290254d3a72SBiju Das rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRA, &pv,
291254d3a72SBiju Das RZ_MTU3_TGRB, &dc);
292254d3a72SBiju Das else
293254d3a72SBiju Das rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRC, &pv,
294254d3a72SBiju Das RZ_MTU3_TGRD, &dc);
295254d3a72SBiju Das
296254d3a72SBiju Das val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR);
297254d3a72SBiju Das prescale = FIELD_GET(RZ_MTU3_TCR_TPCS, val);
298254d3a72SBiju Das
299254d3a72SBiju Das /* With prescale <= 7 and pv <= 0xffff this doesn't overflow. */
300254d3a72SBiju Das tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale);
301254d3a72SBiju Das state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
302254d3a72SBiju Das tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale);
303254d3a72SBiju Das state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
304254d3a72SBiju Das
305254d3a72SBiju Das if (state->duty_cycle > state->period)
306254d3a72SBiju Das state->duty_cycle = state->period;
307254d3a72SBiju Das }
308254d3a72SBiju Das
309254d3a72SBiju Das state->polarity = PWM_POLARITY_NORMAL;
310254d3a72SBiju Das pm_runtime_put(chip->dev);
311254d3a72SBiju Das
312254d3a72SBiju Das return 0;
313254d3a72SBiju Das }
314254d3a72SBiju Das
rz_mtu3_pwm_calculate_pv_or_dc(u64 period_or_duty_cycle,u8 prescale)315254d3a72SBiju Das static u16 rz_mtu3_pwm_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
316254d3a72SBiju Das {
317254d3a72SBiju Das return min(period_or_duty_cycle >> (2 * prescale), (u64)U16_MAX);
318254d3a72SBiju Das }
319254d3a72SBiju Das
rz_mtu3_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)320254d3a72SBiju Das static int rz_mtu3_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
321254d3a72SBiju Das const struct pwm_state *state)
322254d3a72SBiju Das {
323254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
324254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv;
325254d3a72SBiju Das u64 period_cycles;
326254d3a72SBiju Das u64 duty_cycles;
327254d3a72SBiju Das u8 prescale;
328254d3a72SBiju Das u16 pv, dc;
329254d3a72SBiju Das u8 val;
330254d3a72SBiju Das u32 ch;
331254d3a72SBiju Das
332254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
333254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data;
334254d3a72SBiju Das
335254d3a72SBiju Das period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate,
336254d3a72SBiju Das NSEC_PER_SEC);
337254d3a72SBiju Das prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles);
338254d3a72SBiju Das
339254d3a72SBiju Das /*
340254d3a72SBiju Das * Prescalar is shared by multiple channels, so prescale can
341254d3a72SBiju Das * NOT be modified when there are multiple channels in use with
342254d3a72SBiju Das * different settings. Modify prescalar if other PWM is off or handle
343254d3a72SBiju Das * it, if current prescale value is less than the one we want to set.
344254d3a72SBiju Das */
345254d3a72SBiju Das if (rz_mtu3_pwm->enable_count[ch] > 1) {
346254d3a72SBiju Das if (rz_mtu3_pwm->prescale[ch] > prescale)
347254d3a72SBiju Das return -EBUSY;
348254d3a72SBiju Das
349254d3a72SBiju Das prescale = rz_mtu3_pwm->prescale[ch];
350254d3a72SBiju Das }
351254d3a72SBiju Das
352254d3a72SBiju Das pv = rz_mtu3_pwm_calculate_pv_or_dc(period_cycles, prescale);
353254d3a72SBiju Das
354254d3a72SBiju Das duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate,
355254d3a72SBiju Das NSEC_PER_SEC);
356254d3a72SBiju Das dc = rz_mtu3_pwm_calculate_pv_or_dc(duty_cycles, prescale);
357254d3a72SBiju Das
358254d3a72SBiju Das /*
359254d3a72SBiju Das * If the PWM channel is disabled, make sure to turn on the clock
360254d3a72SBiju Das * before writing the register.
361254d3a72SBiju Das */
362254d3a72SBiju Das if (!pwm->state.enabled) {
363254d3a72SBiju Das int rc;
364254d3a72SBiju Das
365254d3a72SBiju Das rc = pm_runtime_resume_and_get(chip->dev);
366254d3a72SBiju Das if (rc)
367254d3a72SBiju Das return rc;
368254d3a72SBiju Das }
369254d3a72SBiju Das
370254d3a72SBiju Das val = RZ_MTU3_TCR_CKEG_RISING | prescale;
371254d3a72SBiju Das
372254d3a72SBiju Das /* Counter must be stopped while updating TCR register */
373254d3a72SBiju Das if (rz_mtu3_pwm->prescale[ch] != prescale && rz_mtu3_pwm->enable_count[ch])
374254d3a72SBiju Das rz_mtu3_disable(priv->mtu);
375254d3a72SBiju Das
376254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm) {
377254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,
378254d3a72SBiju Das RZ_MTU3_TCR_CCLR_TGRA | val);
379254d3a72SBiju Das rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRA, pv,
380254d3a72SBiju Das RZ_MTU3_TGRB, dc);
381254d3a72SBiju Das } else {
382254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,
383254d3a72SBiju Das RZ_MTU3_TCR_CCLR_TGRC | val);
384254d3a72SBiju Das rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRC, pv,
385254d3a72SBiju Das RZ_MTU3_TGRD, dc);
386254d3a72SBiju Das }
387254d3a72SBiju Das
388254d3a72SBiju Das if (rz_mtu3_pwm->prescale[ch] != prescale) {
389254d3a72SBiju Das /*
390254d3a72SBiju Das * Prescalar is shared by multiple channels, we cache the
391254d3a72SBiju Das * prescalar value from first enabled channel and use the same
392254d3a72SBiju Das * value for both channels.
393254d3a72SBiju Das */
394254d3a72SBiju Das rz_mtu3_pwm->prescale[ch] = prescale;
395254d3a72SBiju Das
396254d3a72SBiju Das if (rz_mtu3_pwm->enable_count[ch])
397254d3a72SBiju Das rz_mtu3_enable(priv->mtu);
398254d3a72SBiju Das }
399254d3a72SBiju Das
400254d3a72SBiju Das /* If the PWM is not enabled, turn the clock off again to save power. */
401254d3a72SBiju Das if (!pwm->state.enabled)
402254d3a72SBiju Das pm_runtime_put(chip->dev);
403254d3a72SBiju Das
404254d3a72SBiju Das return 0;
405254d3a72SBiju Das }
406254d3a72SBiju Das
rz_mtu3_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)407254d3a72SBiju Das static int rz_mtu3_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
408254d3a72SBiju Das const struct pwm_state *state)
409254d3a72SBiju Das {
410254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
411254d3a72SBiju Das bool enabled = pwm->state.enabled;
412254d3a72SBiju Das int ret;
413254d3a72SBiju Das
414254d3a72SBiju Das if (state->polarity != PWM_POLARITY_NORMAL)
415254d3a72SBiju Das return -EINVAL;
416254d3a72SBiju Das
417254d3a72SBiju Das if (!state->enabled) {
418254d3a72SBiju Das if (enabled)
419254d3a72SBiju Das rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm);
420254d3a72SBiju Das
421254d3a72SBiju Das return 0;
422254d3a72SBiju Das }
423254d3a72SBiju Das
424254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock);
425254d3a72SBiju Das ret = rz_mtu3_pwm_config(chip, pwm, state);
426254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock);
427254d3a72SBiju Das if (ret)
428254d3a72SBiju Das return ret;
429254d3a72SBiju Das
430254d3a72SBiju Das if (!enabled)
431254d3a72SBiju Das ret = rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm);
432254d3a72SBiju Das
433254d3a72SBiju Das return ret;
434254d3a72SBiju Das }
435254d3a72SBiju Das
436254d3a72SBiju Das static const struct pwm_ops rz_mtu3_pwm_ops = {
437254d3a72SBiju Das .request = rz_mtu3_pwm_request,
438254d3a72SBiju Das .free = rz_mtu3_pwm_free,
439254d3a72SBiju Das .get_state = rz_mtu3_pwm_get_state,
440254d3a72SBiju Das .apply = rz_mtu3_pwm_apply,
441254d3a72SBiju Das .owner = THIS_MODULE,
442254d3a72SBiju Das };
443254d3a72SBiju Das
rz_mtu3_pwm_pm_runtime_suspend(struct device * dev)444254d3a72SBiju Das static int rz_mtu3_pwm_pm_runtime_suspend(struct device *dev)
445254d3a72SBiju Das {
446254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev);
447254d3a72SBiju Das
448254d3a72SBiju Das clk_disable_unprepare(rz_mtu3_pwm->clk);
449254d3a72SBiju Das
450254d3a72SBiju Das return 0;
451254d3a72SBiju Das }
452254d3a72SBiju Das
rz_mtu3_pwm_pm_runtime_resume(struct device * dev)453254d3a72SBiju Das static int rz_mtu3_pwm_pm_runtime_resume(struct device *dev)
454254d3a72SBiju Das {
455254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev);
456254d3a72SBiju Das
457254d3a72SBiju Das return clk_prepare_enable(rz_mtu3_pwm->clk);
458254d3a72SBiju Das }
459254d3a72SBiju Das
460254d3a72SBiju Das static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_pwm_pm_ops,
461254d3a72SBiju Das rz_mtu3_pwm_pm_runtime_suspend,
462254d3a72SBiju Das rz_mtu3_pwm_pm_runtime_resume, NULL);
463254d3a72SBiju Das
rz_mtu3_pwm_pm_disable(void * data)464254d3a72SBiju Das static void rz_mtu3_pwm_pm_disable(void *data)
465254d3a72SBiju Das {
466254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = data;
467254d3a72SBiju Das
468254d3a72SBiju Das clk_rate_exclusive_put(rz_mtu3_pwm->clk);
469254d3a72SBiju Das pm_runtime_disable(rz_mtu3_pwm->chip.dev);
470254d3a72SBiju Das pm_runtime_set_suspended(rz_mtu3_pwm->chip.dev);
471254d3a72SBiju Das }
472254d3a72SBiju Das
rz_mtu3_pwm_probe(struct platform_device * pdev)473254d3a72SBiju Das static int rz_mtu3_pwm_probe(struct platform_device *pdev)
474254d3a72SBiju Das {
475254d3a72SBiju Das struct rz_mtu3 *parent_ddata = dev_get_drvdata(pdev->dev.parent);
476254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm;
477254d3a72SBiju Das struct device *dev = &pdev->dev;
478254d3a72SBiju Das unsigned int i, j = 0;
479254d3a72SBiju Das int ret;
480254d3a72SBiju Das
481254d3a72SBiju Das rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL);
482254d3a72SBiju Das if (!rz_mtu3_pwm)
483254d3a72SBiju Das return -ENOMEM;
484254d3a72SBiju Das
485254d3a72SBiju Das rz_mtu3_pwm->clk = parent_ddata->clk;
486254d3a72SBiju Das
487254d3a72SBiju Das for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {
488254d3a72SBiju Das if (i == RZ_MTU3_CHAN_5 || i == RZ_MTU3_CHAN_8)
489254d3a72SBiju Das continue;
490254d3a72SBiju Das
491254d3a72SBiju Das rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i];
492254d3a72SBiju Das rz_mtu3_pwm->channel_data[j].mtu->dev = dev;
493254d3a72SBiju Das rz_mtu3_pwm->channel_data[j].map = &channel_map[j];
494254d3a72SBiju Das j++;
495254d3a72SBiju Das }
496254d3a72SBiju Das
497254d3a72SBiju Das mutex_init(&rz_mtu3_pwm->lock);
498254d3a72SBiju Das platform_set_drvdata(pdev, rz_mtu3_pwm);
499254d3a72SBiju Das ret = clk_prepare_enable(rz_mtu3_pwm->clk);
500254d3a72SBiju Das if (ret)
501254d3a72SBiju Das return dev_err_probe(dev, ret, "Clock enable failed\n");
502254d3a72SBiju Das
503254d3a72SBiju Das clk_rate_exclusive_get(rz_mtu3_pwm->clk);
504254d3a72SBiju Das
505254d3a72SBiju Das rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk);
506254d3a72SBiju Das /*
507254d3a72SBiju Das * Refuse clk rates > 1 GHz to prevent overflow later for computing
508254d3a72SBiju Das * period and duty cycle.
509254d3a72SBiju Das */
510254d3a72SBiju Das if (rz_mtu3_pwm->rate > NSEC_PER_SEC) {
511254d3a72SBiju Das ret = -EINVAL;
512254d3a72SBiju Das clk_rate_exclusive_put(rz_mtu3_pwm->clk);
513254d3a72SBiju Das goto disable_clock;
514254d3a72SBiju Das }
515254d3a72SBiju Das
516254d3a72SBiju Das pm_runtime_set_active(&pdev->dev);
517254d3a72SBiju Das pm_runtime_enable(&pdev->dev);
518254d3a72SBiju Das rz_mtu3_pwm->chip.dev = &pdev->dev;
519254d3a72SBiju Das ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_pwm_pm_disable,
520254d3a72SBiju Das rz_mtu3_pwm);
521254d3a72SBiju Das if (ret < 0)
522254d3a72SBiju Das return ret;
523254d3a72SBiju Das
524254d3a72SBiju Das rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops;
525254d3a72SBiju Das rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_CHANNELS;
526254d3a72SBiju Das ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip);
527254d3a72SBiju Das if (ret)
528254d3a72SBiju Das return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
529254d3a72SBiju Das
530254d3a72SBiju Das pm_runtime_idle(&pdev->dev);
531254d3a72SBiju Das
532254d3a72SBiju Das return 0;
533254d3a72SBiju Das
534254d3a72SBiju Das disable_clock:
535254d3a72SBiju Das clk_disable_unprepare(rz_mtu3_pwm->clk);
536254d3a72SBiju Das return ret;
537254d3a72SBiju Das }
538254d3a72SBiju Das
539254d3a72SBiju Das static struct platform_driver rz_mtu3_pwm_driver = {
540254d3a72SBiju Das .driver = {
541254d3a72SBiju Das .name = "pwm-rz-mtu3",
542254d3a72SBiju Das .pm = pm_ptr(&rz_mtu3_pwm_pm_ops),
543254d3a72SBiju Das },
544254d3a72SBiju Das .probe = rz_mtu3_pwm_probe,
545254d3a72SBiju Das };
546254d3a72SBiju Das module_platform_driver(rz_mtu3_pwm_driver);
547254d3a72SBiju Das
548254d3a72SBiju Das MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
549254d3a72SBiju Das MODULE_ALIAS("platform:pwm-rz-mtu3");
550254d3a72SBiju Das MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a PWM Timer Driver");
551254d3a72SBiju Das MODULE_LICENSE("GPL");
552