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/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-clk-ccf.dtsi193 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
198 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
203 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
208 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dqcom-emac.txt44 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
93 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
H A Dcdns,macb.yaml83 - enum: [ rx_clk, tsu_clk ]
210 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
H A Dqca,ar803x.yaml47 cable is disconnected. And the RX_CLK always keeps outputting a
H A Dmotorcomm,yt8xxx.yaml57 drive strength of rx_clk rgmii pad.
/openbmc/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c478 struct clk **rx_clk, struct clk **rxs_clk);
496 * @rx_clk: DMA s2mm clock
515 struct clk *rx_clk; member
2616 struct clk **tx_clk, struct clk **rx_clk, in axidma_clk_init() argument
2631 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); in axidma_clk_init()
2632 if (IS_ERR(*rx_clk)) in axidma_clk_init()
2633 *rx_clk = NULL; in axidma_clk_init()
2651 err = clk_prepare_enable(*rx_clk); in axidma_clk_init()
2653 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in axidma_clk_init()
2666 clk_disable_unprepare(*rx_clk); in axidma_clk_init()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/stv0991/
H A Dclock.c32 /* Clock selection for ethernet tx_clk & rx_clk*/ in clock_setup()
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c61 * cleared on both, the falling and rising edge of the RX_CLK. This selects the
73 /* Defined for adding a delay to the input RX_CLK for better timing.
76 * adjust the window between RX_CLK and RX_DATA and improve the stability
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dpincfg.txt52 0 0 2 0 1 0 /* RX_CLK */
/openbmc/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c3961 struct clk *rx_clk, struct clk *tsu_clk) in macb_clks_disable() argument
3965 { .clk = rx_clk, }, in macb_clks_disable()
3976 struct clk **rx_clk, struct clk **tsu_clk) in macb_clk_init() argument
4004 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk"); in macb_clk_init()
4005 if (IS_ERR(*rx_clk)) in macb_clk_init()
4006 return PTR_ERR(*rx_clk); in macb_clk_init()
4030 err = clk_prepare_enable(*rx_clk); in macb_clk_init()
4032 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in macb_clk_init()
4045 clk_disable_unprepare(*rx_clk); in macb_clk_init()
4554 struct clk **rx_clk, struct clk **tsu_clk) in at91ether_clk_init() argument
[all …]
H A Dmacb.h1191 struct clk **rx_clk, struct clk **tsu_clk);
1270 struct clk *rx_clk; member
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dmpc8568mds.c46 {4, 17, 2, 0, 2}, /* RX_CLK */
71 {5, 17, 2, 0, 2}, /* RX_CLK */
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8568mds.dts148 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
176 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
/openbmc/u-boot/board/liebherr/mccmon6/
H A Dmccmon6.c388 * RX_CLK Pad Skew 0xF -> 0.9 nsec skew in board_phy_config()
392 * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew in board_phy_config()
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts179 3 21 2 0 1 0 /* RX_CLK (CLK16) */
199 0 13 2 0 1 0 /* RX_CLK (CLK9) */
H A Dkmeter1.dts163 0 0 2 0 1 0 /* RX_CLK */
189 0 31 2 0 1 0 /* RX_CLK */
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi586 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
602 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
618 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
634 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c444 pad_mii_rx.clk_os = 2; /* RX_CLK/RXC output stage: */ in sja1105_cfg_pad_rx_config()
446 pad_mii_rx.clk_ih = 0; /* RX_CLK/RXC input hysteresis: */ in sja1105_cfg_pad_rx_config()
448 pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */ in sja1105_cfg_pad_rx_config()
/openbmc/linux/drivers/net/phy/
H A Dmicrel.c909 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
915 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
1007 u16 rx, tx, rx_clk, tx_clk; in ksz9031_config_rgmii_delay() local
1015 rx_clk = RX_CLK_ND; in ksz9031_config_rgmii_delay()
1021 rx_clk = RX_CLK_ID; in ksz9031_config_rgmii_delay()
1027 rx_clk = RX_CLK_ID; in ksz9031_config_rgmii_delay()
1033 rx_clk = RX_CLK_ND; in ksz9031_config_rgmii_delay()
1063 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); in ksz9031_config_rgmii_delay()
H A Dicplus.c35 #define IP1001_RXPHASE_SEL BIT(0) /* Add delay on RX_CLK */
/openbmc/u-boot/board/keymile/km83xx/
H A Dkm83xx.c52 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
/openbmc/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac.c69 "rx_clk", "sys_clk"
/openbmc/u-boot/board/freescale/mpc8555cds/
H A Dmpc8555cds.c122 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/openbmc/u-boot/board/freescale/mpc8541cds/
H A Dmpc8541cds.c124 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/openbmc/qemu/hw/arm/
H A Dxlnx-versal-virt.c292 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; in fdt_add_gem_nodes()

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