1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2415a613bSKumar Gala /*
3568336ecSchenhui zhao * Copyright 2004, 2011 Freescale Semiconductor.
4415a613bSKumar Gala *
5415a613bSKumar Gala * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6415a613bSKumar Gala */
7415a613bSKumar Gala
8415a613bSKumar Gala #include <common.h>
9415a613bSKumar Gala #include <pci.h>
10415a613bSKumar Gala #include <asm/processor.h>
11aa11d85cSJon Loeliger #include <asm/mmu.h>
12415a613bSKumar Gala #include <asm/immap_85xx.h>
135614e71bSYork Sun #include <fsl_ddr_sdram.h>
14415a613bSKumar Gala #include <ioports.h>
15a30a549aSJon Loeliger #include <spd_sdram.h>
16b08c8c48SMasahiro Yamada #include <linux/libfdt.h>
17415a613bSKumar Gala #include <fdt_support.h>
18415a613bSKumar Gala
19415a613bSKumar Gala #include "../common/cadmus.h"
20415a613bSKumar Gala #include "../common/eeprom.h"
21415a613bSKumar Gala #include "../common/via.h"
22415a613bSKumar Gala
23415a613bSKumar Gala #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
24415a613bSKumar Gala extern void ddr_enable_ecc(unsigned int dram_size);
25415a613bSKumar Gala #endif
26415a613bSKumar Gala
27415a613bSKumar Gala void local_bus_init(void);
28415a613bSKumar Gala
29415a613bSKumar Gala /*
30415a613bSKumar Gala * I/O Port configuration table
31415a613bSKumar Gala *
32415a613bSKumar Gala * if conf is 1, then that port pin will be configured at boot time
33415a613bSKumar Gala * according to the five values podr/pdir/ppar/psor/pdat for that entry
34415a613bSKumar Gala */
35415a613bSKumar Gala
36415a613bSKumar Gala const iop_conf_t iop_conf_tab[4][32] = {
37415a613bSKumar Gala
38415a613bSKumar Gala /* Port A configuration */
39415a613bSKumar Gala { /* conf ppar psor pdir podr pdat */
40415a613bSKumar Gala /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
41415a613bSKumar Gala /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
42415a613bSKumar Gala /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
43415a613bSKumar Gala /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
44415a613bSKumar Gala /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
45415a613bSKumar Gala /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
46415a613bSKumar Gala /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
47415a613bSKumar Gala /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
48415a613bSKumar Gala /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
49415a613bSKumar Gala /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
50415a613bSKumar Gala /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
51415a613bSKumar Gala /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
52415a613bSKumar Gala /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
53415a613bSKumar Gala /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
54415a613bSKumar Gala /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
55415a613bSKumar Gala /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
56415a613bSKumar Gala /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
57415a613bSKumar Gala /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
58415a613bSKumar Gala /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
59415a613bSKumar Gala /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
60415a613bSKumar Gala /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
61415a613bSKumar Gala /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
62415a613bSKumar Gala /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
63415a613bSKumar Gala /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
64415a613bSKumar Gala /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
65415a613bSKumar Gala /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
66415a613bSKumar Gala /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
67415a613bSKumar Gala /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
68415a613bSKumar Gala /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
69415a613bSKumar Gala /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
70415a613bSKumar Gala /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
71415a613bSKumar Gala /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
72415a613bSKumar Gala },
73415a613bSKumar Gala
74415a613bSKumar Gala /* Port B configuration */
75415a613bSKumar Gala { /* conf ppar psor pdir podr pdat */
76415a613bSKumar Gala /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
77415a613bSKumar Gala /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
78415a613bSKumar Gala /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
79415a613bSKumar Gala /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
80415a613bSKumar Gala /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
81415a613bSKumar Gala /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
82415a613bSKumar Gala /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
83415a613bSKumar Gala /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
84415a613bSKumar Gala /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
85415a613bSKumar Gala /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
86415a613bSKumar Gala /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
87415a613bSKumar Gala /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
88415a613bSKumar Gala /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
89415a613bSKumar Gala /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
90415a613bSKumar Gala /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
91415a613bSKumar Gala /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
92415a613bSKumar Gala /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
93415a613bSKumar Gala /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
94415a613bSKumar Gala /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
95415a613bSKumar Gala /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
96415a613bSKumar Gala /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
97415a613bSKumar Gala /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
98415a613bSKumar Gala /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
99415a613bSKumar Gala /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
100415a613bSKumar Gala /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
101415a613bSKumar Gala /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
102415a613bSKumar Gala /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
103415a613bSKumar Gala /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
104415a613bSKumar Gala /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
105415a613bSKumar Gala /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
106415a613bSKumar Gala /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
107415a613bSKumar Gala /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
108415a613bSKumar Gala },
109415a613bSKumar Gala
110415a613bSKumar Gala /* Port C */
111415a613bSKumar Gala { /* conf ppar psor pdir podr pdat */
112415a613bSKumar Gala /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
113415a613bSKumar Gala /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
114415a613bSKumar Gala /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
115415a613bSKumar Gala /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
116415a613bSKumar Gala /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
117415a613bSKumar Gala /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
118415a613bSKumar Gala /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
119415a613bSKumar Gala /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
120415a613bSKumar Gala /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
121415a613bSKumar Gala /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
122415a613bSKumar Gala /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
123415a613bSKumar Gala /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
124415a613bSKumar Gala /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
125415a613bSKumar Gala /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
126415a613bSKumar Gala /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
127415a613bSKumar Gala /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
128415a613bSKumar Gala /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
129415a613bSKumar Gala /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
130415a613bSKumar Gala /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
131415a613bSKumar Gala /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
132415a613bSKumar Gala /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
133415a613bSKumar Gala /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
134415a613bSKumar Gala /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
135415a613bSKumar Gala /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
136415a613bSKumar Gala /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
137415a613bSKumar Gala /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
138415a613bSKumar Gala /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
139415a613bSKumar Gala /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
140415a613bSKumar Gala /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
141415a613bSKumar Gala /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
142415a613bSKumar Gala /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
143415a613bSKumar Gala /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
144415a613bSKumar Gala },
145415a613bSKumar Gala
146415a613bSKumar Gala /* Port D */
147415a613bSKumar Gala { /* conf ppar psor pdir podr pdat */
148415a613bSKumar Gala /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
149415a613bSKumar Gala /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
150415a613bSKumar Gala /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
151415a613bSKumar Gala /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
152415a613bSKumar Gala /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
153415a613bSKumar Gala /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
154415a613bSKumar Gala /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
155415a613bSKumar Gala /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
156415a613bSKumar Gala /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
157415a613bSKumar Gala /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
158415a613bSKumar Gala /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
159415a613bSKumar Gala /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
160415a613bSKumar Gala /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
161415a613bSKumar Gala /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
162415a613bSKumar Gala /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
163415a613bSKumar Gala /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
164415a613bSKumar Gala /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
165415a613bSKumar Gala /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
166415a613bSKumar Gala /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
167415a613bSKumar Gala /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
168415a613bSKumar Gala /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
169415a613bSKumar Gala /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
170415a613bSKumar Gala /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
171415a613bSKumar Gala /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
172415a613bSKumar Gala /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
173415a613bSKumar Gala /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
174415a613bSKumar Gala /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
175415a613bSKumar Gala /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
176415a613bSKumar Gala /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
177415a613bSKumar Gala /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
178415a613bSKumar Gala /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
179415a613bSKumar Gala /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
180415a613bSKumar Gala }
181415a613bSKumar Gala };
182415a613bSKumar Gala
checkboard(void)183415a613bSKumar Gala int checkboard (void)
184415a613bSKumar Gala {
1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
186568336ecSchenhui zhao char buf[32];
187415a613bSKumar Gala
188415a613bSKumar Gala /* PCI slot in USER bits CSR[6:7] by convention. */
189415a613bSKumar Gala uint pci_slot = get_pci_slot ();
190415a613bSKumar Gala
191415a613bSKumar Gala uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
192415a613bSKumar Gala uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
193415a613bSKumar Gala uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
194415a613bSKumar Gala uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
195415a613bSKumar Gala
196415a613bSKumar Gala uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
197415a613bSKumar Gala
198415a613bSKumar Gala uint cpu_board_rev = get_cpu_board_revision ();
199415a613bSKumar Gala
200415a613bSKumar Gala printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
201415a613bSKumar Gala get_board_version (), pci_slot);
202415a613bSKumar Gala
203415a613bSKumar Gala printf ("CPU Board Revision %d.%d (0x%04x)\n",
204415a613bSKumar Gala MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
205415a613bSKumar Gala MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
206415a613bSKumar Gala
207415a613bSKumar Gala printf("PCI1: %d bit, %s MHz, %s\n",
208415a613bSKumar Gala (pci1_32) ? 32 : 64,
209568336ecSchenhui zhao strmhz(buf, pci1_speed),
210415a613bSKumar Gala pci1_clk_sel ? "sync" : "async");
211415a613bSKumar Gala
212415a613bSKumar Gala if (pci_dual) {
213415a613bSKumar Gala printf("PCI2: 32 bit, 66 MHz, %s\n",
214415a613bSKumar Gala pci2_clk_sel ? "sync" : "async");
215415a613bSKumar Gala } else {
216415a613bSKumar Gala printf("PCI2: disabled\n");
217415a613bSKumar Gala }
218415a613bSKumar Gala
219415a613bSKumar Gala /*
220415a613bSKumar Gala * Initialize local bus.
221415a613bSKumar Gala */
222415a613bSKumar Gala local_bus_init ();
223415a613bSKumar Gala
224415a613bSKumar Gala return 0;
225415a613bSKumar Gala }
226415a613bSKumar Gala
227415a613bSKumar Gala /*
228415a613bSKumar Gala * Initialize Local Bus
229415a613bSKumar Gala */
230415a613bSKumar Gala void
local_bus_init(void)231415a613bSKumar Gala local_bus_init(void)
232415a613bSKumar Gala {
2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
234f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
235415a613bSKumar Gala
236415a613bSKumar Gala uint clkdiv;
237415a613bSKumar Gala uint lbc_hz;
238415a613bSKumar Gala sys_info_t sysinfo;
239415a613bSKumar Gala uint temp_lbcdll;
240415a613bSKumar Gala
241415a613bSKumar Gala /*
242415a613bSKumar Gala * Errata LBC11.
243415a613bSKumar Gala * Fix Local Bus clock glitch when DLL is enabled.
244415a613bSKumar Gala *
2458ed44d91SWolfgang Denk * If localbus freq is < 66MHz, DLL bypass mode must be used.
2468ed44d91SWolfgang Denk * If localbus freq is > 133MHz, DLL can be safely enabled.
247415a613bSKumar Gala * Between 66 and 133, the DLL is enabled with an override workaround.
248415a613bSKumar Gala */
249415a613bSKumar Gala
250415a613bSKumar Gala get_sys_info(&sysinfo);
251a5d212a2STrent Piepho clkdiv = lbc->lcrr & LCRR_CLKDIV;
252997399faSPrabhakar Kushwaha lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
253415a613bSKumar Gala
254415a613bSKumar Gala if (lbc_hz < 66) {
255a2af6a7aSPaul Gortmaker lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
256415a613bSKumar Gala
257415a613bSKumar Gala } else if (lbc_hz >= 133) {
258a2af6a7aSPaul Gortmaker lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
259415a613bSKumar Gala
260415a613bSKumar Gala } else {
261a2af6a7aSPaul Gortmaker lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
262415a613bSKumar Gala udelay(200);
263415a613bSKumar Gala
264415a613bSKumar Gala /*
265415a613bSKumar Gala * Sample LBC DLL ctrl reg, upshift it to set the
266415a613bSKumar Gala * override bits.
267415a613bSKumar Gala */
268415a613bSKumar Gala temp_lbcdll = gur->lbcdllcr;
269415a613bSKumar Gala gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
270415a613bSKumar Gala asm("sync;isync;msync");
271415a613bSKumar Gala }
272415a613bSKumar Gala }
273415a613bSKumar Gala
274415a613bSKumar Gala /*
275415a613bSKumar Gala * Initialize SDRAM memory on the Local Bus.
276415a613bSKumar Gala */
lbc_sdram_init(void)27770961ba4SBecky Bruce void lbc_sdram_init(void)
278415a613bSKumar Gala {
2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
280415a613bSKumar Gala
281415a613bSKumar Gala uint idx;
282f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
284415a613bSKumar Gala uint cpu_board_rev;
285415a613bSKumar Gala uint lsdmr_common;
286415a613bSKumar Gala
2877ea3871eSBecky Bruce puts("LBC SDRAM: ");
2887ea3871eSBecky Bruce print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
2897ea3871eSBecky Bruce "\n ");
290415a613bSKumar Gala
291415a613bSKumar Gala /*
292415a613bSKumar Gala * Setup SDRAM Base and Option Registers
293415a613bSKumar Gala */
294f51cdaf1SBecky Bruce set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
295f51cdaf1SBecky Bruce set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lbcr = CONFIG_SYS_LBC_LBCR;
297415a613bSKumar Gala asm("msync");
298415a613bSKumar Gala
2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsrt = CONFIG_SYS_LBC_LSRT;
3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
301415a613bSKumar Gala asm("msync");
302415a613bSKumar Gala
303415a613bSKumar Gala /*
304415a613bSKumar Gala * Determine which address lines to use baed on CPU board rev.
305415a613bSKumar Gala */
306415a613bSKumar Gala cpu_board_rev = get_cpu_board_revision();
3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
308415a613bSKumar Gala if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
309b0fe93edSKumar Gala lsdmr_common |= LSDMR_BSMA1617;
310415a613bSKumar Gala } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
311b0fe93edSKumar Gala lsdmr_common |= LSDMR_BSMA1516;
312415a613bSKumar Gala } else {
313415a613bSKumar Gala /*
314415a613bSKumar Gala * Assume something unable to identify itself is
315415a613bSKumar Gala * really old, and likely has lines 16/17 mapped.
316415a613bSKumar Gala */
317b0fe93edSKumar Gala lsdmr_common |= LSDMR_BSMA1617;
318415a613bSKumar Gala }
319415a613bSKumar Gala
320415a613bSKumar Gala /*
321415a613bSKumar Gala * Issue PRECHARGE ALL command.
322415a613bSKumar Gala */
323b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
324415a613bSKumar Gala asm("sync;msync");
325415a613bSKumar Gala *sdram_addr = 0xff;
326415a613bSKumar Gala ppcDcbf((unsigned long) sdram_addr);
327415a613bSKumar Gala udelay(100);
328415a613bSKumar Gala
329415a613bSKumar Gala /*
330415a613bSKumar Gala * Issue 8 AUTO REFRESH commands.
331415a613bSKumar Gala */
332415a613bSKumar Gala for (idx = 0; idx < 8; idx++) {
333b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
334415a613bSKumar Gala asm("sync;msync");
335415a613bSKumar Gala *sdram_addr = 0xff;
336415a613bSKumar Gala ppcDcbf((unsigned long) sdram_addr);
337415a613bSKumar Gala udelay(100);
338415a613bSKumar Gala }
339415a613bSKumar Gala
340415a613bSKumar Gala /*
341415a613bSKumar Gala * Issue 8 MODE-set command.
342415a613bSKumar Gala */
343b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
344415a613bSKumar Gala asm("sync;msync");
345415a613bSKumar Gala *sdram_addr = 0xff;
346415a613bSKumar Gala ppcDcbf((unsigned long) sdram_addr);
347415a613bSKumar Gala udelay(100);
348415a613bSKumar Gala
349415a613bSKumar Gala /*
350415a613bSKumar Gala * Issue NORMAL OP command.
351415a613bSKumar Gala */
352b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
353415a613bSKumar Gala asm("sync;msync");
354415a613bSKumar Gala *sdram_addr = 0xff;
355415a613bSKumar Gala ppcDcbf((unsigned long) sdram_addr);
356415a613bSKumar Gala udelay(200); /* Overkill. Must wait > 200 bus cycles */
357415a613bSKumar Gala
358415a613bSKumar Gala #endif /* enable SDRAM init */
359415a613bSKumar Gala }
360415a613bSKumar Gala
361415a613bSKumar Gala #if defined(CONFIG_PCI)
362415a613bSKumar Gala /* For some reason the Tundra PCI bridge shows up on itself as a
363415a613bSKumar Gala * different device. Work around that by refusing to configure it.
364415a613bSKumar Gala */
dummy_func(struct pci_controller * hose,pci_dev_t dev,struct pci_config_table * tab)365415a613bSKumar Gala void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
366415a613bSKumar Gala
367415a613bSKumar Gala static struct pci_config_table pci_mpc85xxcds_config_table[] = {
368415a613bSKumar Gala {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
369415a613bSKumar Gala {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
370415a613bSKumar Gala {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
371415a613bSKumar Gala mpc85xx_config_via_usbide, {0,0,0}},
372415a613bSKumar Gala {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
373415a613bSKumar Gala mpc85xx_config_via_usb, {0,0,0}},
374415a613bSKumar Gala {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
375415a613bSKumar Gala mpc85xx_config_via_usb2, {0,0,0}},
376415a613bSKumar Gala {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
377415a613bSKumar Gala mpc85xx_config_via_power, {0,0,0}},
378415a613bSKumar Gala {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
379415a613bSKumar Gala mpc85xx_config_via_ac97, {0,0,0}},
380415a613bSKumar Gala {},
381415a613bSKumar Gala };
382415a613bSKumar Gala
383415a613bSKumar Gala static struct pci_controller hose[] = {
384415a613bSKumar Gala { config_table: pci_mpc85xxcds_config_table,},
385415a613bSKumar Gala #ifdef CONFIG_MPC85XX_PCI2
386415a613bSKumar Gala {},
387415a613bSKumar Gala #endif
388415a613bSKumar Gala };
389415a613bSKumar Gala
390415a613bSKumar Gala #endif /* CONFIG_PCI */
391415a613bSKumar Gala
392415a613bSKumar Gala void
pci_init_board(void)393415a613bSKumar Gala pci_init_board(void)
394415a613bSKumar Gala {
395415a613bSKumar Gala #ifdef CONFIG_PCI
396415a613bSKumar Gala pci_mpc85xx_init(hose);
397415a613bSKumar Gala #endif
398415a613bSKumar Gala }
399415a613bSKumar Gala
400415a613bSKumar Gala #if defined(CONFIG_OF_BOARD_SETUP)
401415a613bSKumar Gala void
ft_pci_setup(void * blob,bd_t * bd)402415a613bSKumar Gala ft_pci_setup(void *blob, bd_t *bd)
403415a613bSKumar Gala {
404415a613bSKumar Gala int node, tmp[2];
405415a613bSKumar Gala const char *path;
406415a613bSKumar Gala
407415a613bSKumar Gala node = fdt_path_offset(blob, "/aliases");
408415a613bSKumar Gala tmp[0] = 0;
409415a613bSKumar Gala if (node >= 0) {
410415a613bSKumar Gala #ifdef CONFIG_PCI1
411415a613bSKumar Gala path = fdt_getprop(blob, node, "pci0", NULL);
412415a613bSKumar Gala if (path) {
413415a613bSKumar Gala tmp[1] = hose[0].last_busno - hose[0].first_busno;
414415a613bSKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
415415a613bSKumar Gala }
416415a613bSKumar Gala #endif
417415a613bSKumar Gala #ifdef CONFIG_MPC85XX_PCI2
418415a613bSKumar Gala path = fdt_getprop(blob, node, "pci1", NULL);
419415a613bSKumar Gala if (path) {
420415a613bSKumar Gala tmp[1] = hose[1].last_busno - hose[1].first_busno;
421415a613bSKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
422415a613bSKumar Gala }
423415a613bSKumar Gala #endif
424415a613bSKumar Gala }
425415a613bSKumar Gala }
426415a613bSKumar Gala #endif
427