12c63221cSMichael Walle# SPDX-License-Identifier: GPL-2.0+ 22c63221cSMichael Walle%YAML 1.2 32c63221cSMichael Walle--- 42c63221cSMichael Walle$id: http://devicetree.org/schemas/net/qca,ar803x.yaml# 52c63221cSMichael Walle$schema: http://devicetree.org/meta-schemas/core.yaml# 62c63221cSMichael Walle 72c63221cSMichael Walletitle: Qualcomm Atheros AR803x PHY 82c63221cSMichael Walle 92c63221cSMichael Wallemaintainers: 102c63221cSMichael Walle - Andrew Lunn <andrew@lunn.ch> 112c63221cSMichael Walle - Florian Fainelli <f.fainelli@gmail.com> 122c63221cSMichael Walle - Heiner Kallweit <hkallweit1@gmail.com> 132c63221cSMichael Walle 142c63221cSMichael Walledescription: | 152c63221cSMichael Walle Bindings for Qualcomm Atheros AR803x PHYs 162c63221cSMichael Walle 172c63221cSMichael WalleallOf: 182c63221cSMichael Walle - $ref: ethernet-phy.yaml# 192c63221cSMichael Walle 202c63221cSMichael Walleproperties: 212c63221cSMichael Walle qca,clk-out-frequency: 222c63221cSMichael Walle description: Clock output frequency in Hertz. 233d21a460SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 243d21a460SRob Herring enum: [25000000, 50000000, 62500000, 125000000] 252c63221cSMichael Walle 262c63221cSMichael Walle qca,clk-out-strength: 272c63221cSMichael Walle description: Clock output driver strength. 283d21a460SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 293d21a460SRob Herring enum: [0, 1, 2] 302c63221cSMichael Walle 31623c1329SRussell King qca,disable-smarteee: 32623c1329SRussell King description: Disable Atheros SmartEEE feature. 33623c1329SRussell King type: boolean 34623c1329SRussell King 352c63221cSMichael Walle qca,keep-pll-enabled: 362c63221cSMichael Walle description: | 372c63221cSMichael Walle If set, keep the PLL enabled even if there is no link. Useful if you 382c63221cSMichael Walle want to use the clock output without an ethernet link. 392c63221cSMichael Walle 402c63221cSMichael Walle Only supported on the AR8031. 412c63221cSMichael Walle type: boolean 422c63221cSMichael Walle 432e7f0899SWei Fang qca,disable-hibernation-mode: 442e7f0899SWei Fang description: | 452e7f0899SWei Fang Disable Atheros AR803X PHYs hibernation mode. If present, indicates 462e7f0899SWei Fang that the hardware of PHY will not enter power saving mode when the 472e7f0899SWei Fang cable is disconnected. And the RX_CLK always keeps outputting a 482e7f0899SWei Fang valid clock. 492e7f0899SWei Fang type: boolean 502e7f0899SWei Fang 51623c1329SRussell King qca,smarteee-tw-us-100m: 52623c1329SRussell King description: EEE Tw parameter for 100M links. 53623c1329SRussell King $ref: /schemas/types.yaml#/definitions/uint32 54623c1329SRussell King minimum: 1 55623c1329SRussell King maximum: 255 56623c1329SRussell King 57623c1329SRussell King qca,smarteee-tw-us-1g: 58623c1329SRussell King description: EEE Tw parameter for gigabit links. 59623c1329SRussell King $ref: /schemas/types.yaml#/definitions/uint32 60623c1329SRussell King minimum: 1 61623c1329SRussell King maximum: 255 62623c1329SRussell King 632c63221cSMichael Walle vddio-supply: 642c63221cSMichael Walle description: | 652c63221cSMichael Walle RGMII I/O voltage regulator (see regulator/regulator.yaml). 662c63221cSMichael Walle 672c63221cSMichael Walle The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can 682c63221cSMichael Walle either connect this to the vddio-regulator (1.5V / 1.8V) or the 692c63221cSMichael Walle vddh-regulator (2.5V). 702c63221cSMichael Walle 712c63221cSMichael Walle Only supported on the AR8031. 722c63221cSMichael Walle 732c63221cSMichael Walle vddio-regulator: 742c63221cSMichael Walle type: object 752c63221cSMichael Walle description: 762c63221cSMichael Walle Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V. 773d21a460SRob Herring $ref: /schemas/regulator/regulator.yaml 78*c1b0b611SKrzysztof Kozlowski unevaluatedProperties: false 792c63221cSMichael Walle 802c63221cSMichael Walle vddh-regulator: 812c63221cSMichael Walle type: object 822c63221cSMichael Walle description: 832c63221cSMichael Walle Dummy subnode to model the external connection of the PHY VDDH 842c63221cSMichael Walle regulator to VDDIO. 853d21a460SRob Herring $ref: /schemas/regulator/regulator.yaml 86*c1b0b611SKrzysztof Kozlowski unevaluatedProperties: false 872c63221cSMichael Walle 886fdc6e23SRob HerringunevaluatedProperties: false 896fdc6e23SRob Herring 902c63221cSMichael Walleexamples: 912c63221cSMichael Walle - | 922c63221cSMichael Walle #include <dt-bindings/net/qca-ar803x.h> 932c63221cSMichael Walle 942c63221cSMichael Walle ethernet { 952c63221cSMichael Walle #address-cells = <1>; 962c63221cSMichael Walle #size-cells = <0>; 972c63221cSMichael Walle 982c63221cSMichael Walle phy-mode = "rgmii-id"; 992c63221cSMichael Walle 1002c63221cSMichael Walle ethernet-phy@0 { 1012c63221cSMichael Walle reg = <0>; 1022c63221cSMichael Walle 1032c63221cSMichael Walle qca,clk-out-frequency = <125000000>; 1042c63221cSMichael Walle qca,clk-out-strength = <AR803X_STRENGTH_FULL>; 1052c63221cSMichael Walle 1062c63221cSMichael Walle vddio-supply = <&vddio>; 1072c63221cSMichael Walle 1082c63221cSMichael Walle vddio: vddio-regulator { 1092c63221cSMichael Walle regulator-min-microvolt = <1800000>; 1102c63221cSMichael Walle regulator-max-microvolt = <1800000>; 1112c63221cSMichael Walle }; 1122c63221cSMichael Walle }; 1132c63221cSMichael Walle }; 1142c63221cSMichael Walle - | 1152c63221cSMichael Walle #include <dt-bindings/net/qca-ar803x.h> 1162c63221cSMichael Walle 1172c63221cSMichael Walle ethernet { 1182c63221cSMichael Walle #address-cells = <1>; 1192c63221cSMichael Walle #size-cells = <0>; 1202c63221cSMichael Walle 1212c63221cSMichael Walle phy-mode = "rgmii-id"; 1222c63221cSMichael Walle 1232c63221cSMichael Walle ethernet-phy@0 { 1242c63221cSMichael Walle reg = <0>; 1252c63221cSMichael Walle 1262c63221cSMichael Walle qca,clk-out-frequency = <50000000>; 1272c63221cSMichael Walle qca,keep-pll-enabled; 1282c63221cSMichael Walle 1292c63221cSMichael Walle vddio-supply = <&vddh>; 1302c63221cSMichael Walle 1312c63221cSMichael Walle vddh: vddh-regulator { 1322c63221cSMichael Walle }; 1332c63221cSMichael Walle }; 1342c63221cSMichael Walle }; 135