Home
last modified time | relevance | path

Searched +full:rx +full:- +full:pcs +full:- +full:input (Results 1 – 25 of 45) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
[all …]
H A Dfsl-fman.txt5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
23 - compatible
32 - cell-index
[all …]
/openbmc/linux/drivers/net/pcs/
H A Dpcs-xpcs-nxp.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
5 #include "pcs-xpcs.h"
67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
69 * normal non-inverted behavior, the TX lane polarity must be inverted in the
70 * PCS, via the DIGITAL_CONTROL_2 register.
117 /* Enable input and output resistor terminations for low BER. */ in nxp_sja1110_pma_config()
126 /* Select PCS as transmitter data source. */ in nxp_sja1110_pma_config()
131 /* Program RX PLL feedback divider and reference divider for correct in nxp_sja1110_pma_config()
146 * when an input signal is not present. in nxp_sja1110_pma_config()
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
51 #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
[all …]
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
82 RX completion reg updated.
86 RX Kick == RX complete */
[all …]
H A Dcassini.c1 // SPDX-License-Identifier: GPL-2.0+
13 * load balancing (non-VLAN mode)
16 * page-based RX descriptor engine with separate completion rings
17 * Gigabit support (GMII and PCS interface)
20 * RX is handled by page sized buffers that are attached as fragments to
22 * -- driver allocates pages at a time and keeps reference counts
24 * -- the upper protocol layers assume that the header is in the skb
27 * -- driver appends the rest of the data pages as frags to skbuffs
29 * -- on page reclamation, the driver swaps the page with a spare page.
37 * TX has 4 queues. currently these queues are used in a round-robin
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
58 /** @brief clock recovered from EAVB input */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
192 /** @brief input from Tegra's XTAL_IN */
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-combo.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
26 #include <dt-bindings/phy/phy-qcom-qmp.h>
28 #include "phy-qcom-qmp.h"
29 #include "phy-qcom-qmp-pcs-misc-v3.h"
30 #include "phy-qcom-qmp-pcs-usb-v4.h"
31 #include "phy-qcom-qmp-pcs-usb-v5.h"
32 #include "phy-qcom-qmp-pcs-usb-v6.h"
99 /* set of registers with offsets different per-PHY */
101 /* PCS registers */
[all …]
/openbmc/linux/drivers/ata/
H A Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
98 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
102 HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */
115 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
29 #include <linux/dma-mapping.h>
55 * with fine resolution and binary rollover. This avoid non-monotonic behavior
62 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
70 static int debug = -1;
72 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
74 static int phyaddr = -1;
78 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4)
[all …]
/openbmc/u-boot/drivers/serial/
H A DKconfig11 Select a default baudrate, where "default" has a driver-specific
19 # non-dm serial code
34 in U-Boot.
41 In very space-constrained devices even the full UART driver is too
43 This option enables the full UART in U-Boot, so if is it disabled,
51 In very space-constrained devices even the full UART driver is too
61 In very space-constrained devices even the full UART driver is too
110 bool "Enable RX buffer for serial input"
113 Enable RX buffer support for the serial driver. This enables
114 pasting longer strings, even when the RX FIFO of the UART is
[all …]
/openbmc/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-dev.c9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
125 #include "xgbe-common.h"
129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
138 DBGPR("-->xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
140 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
143 * Convert the input usec value to the watchdog timer value. Each in xgbe_usec_to_riwt()
150 DBGPR("<--xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
161 DBGPR("-->xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
163 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
9 * PD0011-01-14-Meigs-II 2002-12-12
69 * fn = FIFO number, 0-9
78 #define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
79 #define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
80 #define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
84 * bn = bucket number 0-10 (yes, 11 buckets)
114 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
133 * tri-speed are only defined with the version that needs a port number.
[all …]
/openbmc/qemu/hw/net/
H A Dtrace-events3 # allwinner-sun8i-emac.c
6 allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" P…
31 open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x"
32 open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x"
33 open_eth_update_irq(uint32_t v) "IRQ <- 0x%x"
34 open_eth_receive(unsigned len) "RX: len: %u"
36 open_eth_receive_reject(void) "RX: rejected"
37 open_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: 0x%08x, len_flags: 0x%08x"
39 open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x"
40 open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x"
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
511 __le32 mrq; /* Multiple Rx Queues */
529 /* Receive Descriptor - Packet Split */
537 __le32 mrq; /* Multiple Rx Queues */
553 __le16 length[3]; /* length of buffers 1-3 */
[all …]
/openbmc/linux/include/linux/
H A Dethtool.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 * enum ethtool_phys_id_state - indicator state for physical identification
60 ETH_RSS_HASH_TOP_BIT, /* Configurable RSS hash function - Toeplitz */
61 ETH_RSS_HASH_XOR_BIT, /* Configurable RSS hash function - Xor */
62 ETH_RSS_HASH_CRC32_BIT, /* Configurable RSS hash function - Crc32 */
72 * struct kernel_ethtool_ringparam - RX/TX ring configuration
73 * @rx_buf_len: Current length of buffers on the rx ring.
76 * @rx_push: The flag of rx push mode
77 * @cqe_size: Size of TX/RX completion queue event
92 * enum ethtool_supported_ring_param - indicator caps for setting ring params
[all …]
/openbmc/u-boot/drivers/net/
H A De1000.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
36 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
51 writel((value), ((a)->hw_addr + E1000_##reg))
53 readl((a)->hw_addr + E1000_##reg)
55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
349 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
[all …]
/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
12 #include <linux/dma-mapping.h>
55 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
60 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
134 /* Unicast Filter MAC Address Register - Low */
138 /* Unicast Filter MAC Address Register - High */
154 /* PSE Input Queue Reservation Register*/
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A Digb_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
130 "legacy-rx",
139 struct e1000_hw *hw = &adapter->hw; in igb_get_link_ksettings()
140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_get_link_ksettings()
141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; in igb_get_link_ksettings()
146 status = pm_runtime_suspended(&adapter->pdev->dev) ? in igb_get_link_ksettings()
148 if (hw->phy.media_type == e1000_media_type_copper) { in igb_get_link_ksettings()
[all …]
/openbmc/linux/drivers/net/hamradio/
H A Dyam.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * yam.c -- YAM radio modem driver.
61 /* --------------------------------------------------------------------- */
67 /* --------------------------------------------------------------------- */
94 #define DEFAULT_PERS 64 /* 0->255 */
127 /* Rx section */
147 /* --------------------------------------------------------------------- */
175 #define IER_RX 1 /* enable rx interrupt */
184 #define MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */
188 #define MSR_DCTS 0x01 /* Delta CTS input */
[all …]
/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
18 #include <linux/pcs/pcs-xpcs.h>
75 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; in sja1105_is_vlan_configured()
76 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; in sja1105_is_vlan_configured()
83 return -1; in sja1105_is_vlan_configured()
88 struct sja1105_private *priv = ds->priv; in sja1105_drop_untagged()
91 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_drop_untagged()
106 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_pvid_apply()
[all …]

12