18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
28e8e69d6SThomas Gleixner /*
3656e7052SJohn Crispin *
4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7656e7052SJohn Crispin */
8656e7052SJohn Crispin
9656e7052SJohn Crispin #ifndef MTK_ETH_H
10656e7052SJohn Crispin #define MTK_ETH_H
11656e7052SJohn Crispin
129ffee4a8SSean Wang #include <linux/dma-mapping.h>
139ffee4a8SSean Wang #include <linux/netdevice.h>
149ffee4a8SSean Wang #include <linux/of_net.h>
159ffee4a8SSean Wang #include <linux/u64_stats_sync.h>
16c6d4e63eSElena Reshetova #include <linux/refcount.h>
17b8fc9f30SRené van Dorst #include <linux/phylink.h>
18502e84e2SFelix Fietkau #include <linux/rhashtable.h>
19e9229ffdSFelix Fietkau #include <linux/dim.h>
20bc5e93e0SRussell King (Oracle) #include <linux/bitfield.h>
21a9ca9f9cSYunsheng Lin #include <net/page_pool/types.h>
2223233e57SLorenzo Bianconi #include <linux/bpf_trace.h>
23ba37b7caSFelix Fietkau #include "mtk_ppe.h"
24c6d4e63eSElena Reshetova
252d7605a7SFelix Fietkau #define MTK_MAX_DSA_PORTS 7
262d7605a7SFelix Fietkau #define MTK_DSA_PORT_MASK GENMASK(2, 0)
272d7605a7SFelix Fietkau
28f63959c7SFelix Fietkau #define MTK_QDMA_NUM_QUEUES 16
29656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048
30656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536
314fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048
32656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff
33160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_LEN_V2 0xffff
34c30e0b9bSFelix Fietkau #define MTK_QDMA_RING_SIZE 2048
356b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512
364fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
37656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
38656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff
39656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
40656e7052SJohn Crispin NETIF_MSG_PROBE | \
41656e7052SJohn Crispin NETIF_MSG_LINK | \
42656e7052SJohn Crispin NETIF_MSG_TIMER | \
43656e7052SJohn Crispin NETIF_MSG_IFDOWN | \
44656e7052SJohn Crispin NETIF_MSG_IFUP | \
45656e7052SJohn Crispin NETIF_MSG_RX_ERR | \
46656e7052SJohn Crispin NETIF_MSG_TX_ERR)
47656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
48656e7052SJohn Crispin NETIF_F_RXCSUM | \
49656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \
50656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \
51656e7052SJohn Crispin NETIF_F_TSO6 | \
52502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\
53502e84e2SFelix Fietkau NETIF_F_HW_TC)
54296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
5508df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
56ee406810SNelson Chang
5723233e57SLorenzo Bianconi #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM
5823233e57SLorenzo Bianconi #define MTK_PP_PAD (MTK_PP_HEADROOM + \
5923233e57SLorenzo Bianconi SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
6023233e57SLorenzo Bianconi #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
6123233e57SLorenzo Bianconi
628cb42714SLorenzo Bianconi #define MTK_QRX_OFFSET 0x10
638cb42714SLorenzo Bianconi
64ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4
65ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8
66ee406810SNelson Chang
67ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
68ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2
69ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
70ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
71ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */
72ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
73ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64
74ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000
75ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000
76ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
77656e7052SJohn Crispin
7806127504SLorenzo Bianconi /* Frame Engine Global Configuration */
7988c1e6efSDaniel Golle #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
8088c1e6efSDaniel Golle #define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16)
8106127504SLorenzo Bianconi
82656e7052SJohn Crispin /* Frame Engine Global Reset Register */
83656e7052SJohn Crispin #define MTK_RST_GL 0x04
84656e7052SJohn Crispin #define RST_GL_PSE BIT(0)
85656e7052SJohn Crispin
86656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */
87656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08
8806127504SLorenzo Bianconi #define MTK_FE_INT_ENABLE 0x0c
8906127504SLorenzo Bianconi #define MTK_FE_INT_FQ_EMPTY BIT(8)
9006127504SLorenzo Bianconi #define MTK_FE_INT_TSO_FAIL BIT(12)
9106127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ILLEGAL BIT(13)
9206127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ALIGN BIT(14)
9306127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_OV BIT(18)
9406127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_UF BIT(19)
95656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28)
96656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29)
97656e7052SJohn Crispin
98ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */
99ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
100ee406810SNelson Chang
101656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */
102656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20
103656e7052SJohn Crispin
10487e3df49SSean Wang /* CDMP Ingress Control Register */
10587e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400
10687e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0)
10787e3df49SSean Wang
1082d7605a7SFelix Fietkau /* CDMQ Exgress Control Register */
1092d7605a7SFelix Fietkau #define MTK_CDMQ_EG_CTRL 0x1404
1102d7605a7SFelix Fietkau
111160d3a9bSLorenzo Bianconi /* CDMP Ingress Control Register */
112160d3a9bSLorenzo Bianconi #define MTK_CDMP_IG_CTRL 0x400
113160d3a9bSLorenzo Bianconi #define MTK_CDMP_STAG_EN BIT(0)
114160d3a9bSLorenzo Bianconi
115656e7052SJohn Crispin /* CDMP Exgress Control Register */
116656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404
117656e7052SJohn Crispin
118656e7052SJohn Crispin /* GDM Exgress Control Register */
119445eb644SLorenzo Bianconi #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
120445eb644SLorenzo Bianconi 0x540 : 0x500 + (_x * 0x1000); })
121d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24)
122656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22)
123656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21)
124656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20)
1251953f134SLorenzo Bianconi #define MTK_GDMA_STRP_CRC BIT(16)
1268d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0
1278d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777
128656e7052SJohn Crispin
129445eb644SLorenzo Bianconi /* GDM Egress Control Register */
130445eb644SLorenzo Bianconi #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
131445eb644SLorenzo Bianconi 0x544 : 0x504 + (_x * 0x1000); })
132445eb644SLorenzo Bianconi #define MTK_GDMA_XGDM_SEL BIT(31)
133445eb644SLorenzo Bianconi
134656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */
135cfb5677dSDaniel Golle #define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
136cfb5677dSDaniel Golle 0x548 : 0x508 + (_x * 0x1000); })
137656e7052SJohn Crispin
138656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */
139cfb5677dSDaniel Golle #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
140cfb5677dSDaniel Golle 0x54C : 0x50C + (_x * 0x1000); })
141656e7052SJohn Crispin
142ebb1e4f9SDaniel Golle /* Internal SRAM offset */
143ebb1e4f9SDaniel Golle #define MTK_ETH_SRAM_OFFSET 0x40000
144ebb1e4f9SDaniel Golle
145160d3a9bSLorenzo Bianconi /* FE global misc reg*/
146160d3a9bSLorenzo Bianconi #define MTK_FE_GLO_MISC 0x124
147160d3a9bSLorenzo Bianconi
148160d3a9bSLorenzo Bianconi /* PSE Free Queue Flow Control */
149160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG1 0x100
150160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG2 0x104
151160d3a9bSLorenzo Bianconi #define PSE_DROP_CFG 0x108
152f4b2fa2cSFelix Fietkau #define PSE_PPE0_DROP 0x110
153160d3a9bSLorenzo Bianconi
154160d3a9bSLorenzo Bianconi /* PSE Input Queue Reservation Register*/
155160d3a9bSLorenzo Bianconi #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
156160d3a9bSLorenzo Bianconi
157160d3a9bSLorenzo Bianconi /* PSE Output Queue Threshold Register*/
158160d3a9bSLorenzo Bianconi #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
159160d3a9bSLorenzo Bianconi
160160d3a9bSLorenzo Bianconi /* GDM and CDM Threshold */
161160d3a9bSLorenzo Bianconi #define MTK_GDM2_THRES 0x1530
162160d3a9bSLorenzo Bianconi #define MTK_CDMW0_THRES 0x164c
163160d3a9bSLorenzo Bianconi #define MTK_CDMW1_THRES 0x1650
164160d3a9bSLorenzo Bianconi #define MTK_CDME0_THRES 0x1654
165160d3a9bSLorenzo Bianconi #define MTK_CDME1_THRES 0x1658
166160d3a9bSLorenzo Bianconi #define MTK_CDMM_THRES 0x165c
167160d3a9bSLorenzo Bianconi
168ee406810SNelson Chang /* PDMA HW LRO Control Registers */
169ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980
170ee406810SNelson Chang #define MTK_LRO_EN BIT(0)
171ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7)
172160d3a9bSLorenzo Bianconi #define MTK_L3_CKS_UPD_EN_V2 BIT(19)
173ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
174ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
175160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
176ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
177160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
178ee406810SNelson Chang
179ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984
180ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988
181ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c
182ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15)
183ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
184bacfd110SNelson Chang
1858cb42714SLorenzo Bianconi #define MTK_RX_DMA_LRO_EN BIT(8)
186bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10)
187296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4)
188bacfd110SNelson Chang
1898cb42714SLorenzo Bianconi /* PDMA Global Configuration Register */
1908cb42714SLorenzo Bianconi #define MTK_PDMA_LRO_SDL 0x3000
1918cb42714SLorenzo Bianconi #define MTK_RX_CFG_SDL_OFFSET 16
1928cb42714SLorenzo Bianconi
193bacfd110SNelson Chang /* PDMA Reset Index Register */
194bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16)
195ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
196bacfd110SNelson Chang
197bacfd110SNelson Chang /* PDMA Delay Interrupt Register */
198e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
199671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15)
200671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
201e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
202e9229ffdSFelix Fietkau
203e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16)
204e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31)
205e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24
206e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16
207e9229ffdSFelix Fietkau
208e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f
209e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff
210bacfd110SNelson Chang
211ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */
212ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
213ee406810SNelson Chang
214ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */
215ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04
216ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
217ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9)
218ee406810SNelson Chang
219ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */
220ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
221ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
222ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
223ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
224ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
225ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
226ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
227ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
228ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6)
229ee406810SNelson Chang #define MTK_RING_VLD BIT(8)
230ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
231ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
232ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
233ee406810SNelson Chang
234656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */
235f63959c7SFelix Fietkau #define MTK_QTX_OFFSET 0x10
236656e7052SJohn Crispin #define QDMA_RES_THRES 4
237656e7052SJohn Crispin
238f63959c7SFelix Fietkau /* QDMA Tx Queue Scheduler Configuration Registers */
239f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL BIT(31)
240f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30)
241f63959c7SFelix Fietkau
242f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30)
243f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28)
244f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EN BIT(27)
245f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20)
246f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16)
247f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12)
248f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EN BIT(11)
249f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4)
250f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)
251f63959c7SFelix Fietkau
252f63959c7SFelix Fietkau /* QDMA TX Scheduler Rate Control Register */
253f63959c7SFelix Fietkau #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15)
254f63959c7SFelix Fietkau
255656e7052SJohn Crispin /* QDMA Global Configuration Register */
256656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31)
257656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11)
2586675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10)
259656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6)
26059555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4)
261656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3)
262656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1)
263656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2)
264656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0)
2653bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000
266656e7052SJohn Crispin
267160d3a9bSLorenzo Bianconi /* QDMA V2 Global Configuration Register */
268160d3a9bSLorenzo Bianconi #define MTK_CHK_DDONE_EN BIT(28)
269160d3a9bSLorenzo Bianconi #define MTK_DMAD_WR_WDONE BIT(26)
270160d3a9bSLorenzo Bianconi #define MTK_WCOMP_EN BIT(24)
271160d3a9bSLorenzo Bianconi #define MTK_RESV_BUF (0x40 << 16)
272160d3a9bSLorenzo Bianconi #define MTK_MUTLI_CNT (0x4 << 12)
273f63959c7SFelix Fietkau #define MTK_LEAKY_BUCKET_EN BIT(11)
274160d3a9bSLorenzo Bianconi
275656e7052SJohn Crispin /* QDMA Flow Control Register */
276656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20)
277656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16)
278656e7052SJohn Crispin #define FC_THRES_MIN 0x4444
279656e7052SJohn Crispin
280656e7052SJohn Crispin /* QDMA Interrupt Status Register */
281671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30)
282e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28)
283bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19)
284bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18)
285656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17)
286656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16)
287656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3)
288656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2)
289656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1)
290656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0)
291671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY
292e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY
293656e7052SJohn Crispin
294160d3a9bSLorenzo Bianconi #define MTK_RX_DONE_INT_V2 BIT(14)
295160d3a9bSLorenzo Bianconi
29693b2591aSLorenzo Bianconi #define MTK_CDM_TXFIFO_RDY BIT(7)
29793b2591aSLorenzo Bianconi
29880673029SJohn Crispin /* QDMA Interrupt grouping registers */
29980673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0)
30080673029SJohn Crispin
301160d3a9bSLorenzo Bianconi /* QDMA TX NUM */
302160d3a9bSLorenzo Bianconi #define QID_BITS_V2(x) (((x) & 0x3f) << 16)
303160d3a9bSLorenzo Bianconi #define MTK_QDMA_GMAC2_QID 8
304160d3a9bSLorenzo Bianconi
305160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_SHIFT 8
306160d3a9bSLorenzo Bianconi
307160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd6 */
308160d3a9bSLorenzo Bianconi #define TX_DMA_INS_VLAN_V2 BIT(16)
309160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd5 */
310160d3a9bSLorenzo Bianconi #define TX_DMA_CHKSUM_V2 (0x7 << 28)
311160d3a9bSLorenzo Bianconi #define TX_DMA_TSO_V2 BIT(31)
312160d3a9bSLorenzo Bianconi
3131953f134SLorenzo Bianconi #define TX_DMA_SPTAG_V3 BIT(27)
3141953f134SLorenzo Bianconi
315160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd4 */
316160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_SHIFT_V2 8
317160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_MASK_V2 0xf
318160d3a9bSLorenzo Bianconi #define TX_DMA_SWC_V2 BIT(30)
319160d3a9bSLorenzo Bianconi
320656e7052SJohn Crispin /* QDMA descriptor txd4 */
321656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29)
322656e7052SJohn Crispin #define TX_DMA_TSO BIT(28)
323656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25
324656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7
325656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16)
326656e7052SJohn Crispin
327656e7052SJohn Crispin /* QDMA descriptor txd3 */
328656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31)
329656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30)
330160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
331160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len)
332656e7052SJohn Crispin #define TX_DMA_SWC BIT(14)
333f63959c7SFelix Fietkau #define TX_DMA_PQID GENMASK(3, 0)
334*2d75891eSDaniel Golle #define TX_DMA_ADDR64_MASK GENMASK(3, 0)
335*2d75891eSDaniel Golle #if IS_ENABLED(CONFIG_64BIT)
336*2d75891eSDaniel Golle # define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32)
337*2d75891eSDaniel Golle # define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32))
338*2d75891eSDaniel Golle #else
339*2d75891eSDaniel Golle # define TX_DMA_GET_ADDR64(x) (0)
340*2d75891eSDaniel Golle # define TX_DMA_PREP_ADDR64(x) (0)
341*2d75891eSDaniel Golle #endif
342656e7052SJohn Crispin
343296c9120SStefan Roese /* PDMA on MT7628 */
344296c9120SStefan Roese #define TX_DMA_DONE BIT(31)
345296c9120SStefan Roese #define TX_DMA_LS1 BIT(14)
346296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
347296c9120SStefan Roese
348656e7052SJohn Crispin /* QDMA descriptor rxd2 */
349656e7052SJohn Crispin #define RX_DMA_DONE BIT(31)
350296c9120SStefan Roese #define RX_DMA_LSO BIT(30)
351160d3a9bSLorenzo Bianconi #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
352160d3a9bSLorenzo Bianconi #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
3533f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15)
354*2d75891eSDaniel Golle #define RX_DMA_ADDR64_MASK GENMASK(3, 0)
355*2d75891eSDaniel Golle #if IS_ENABLED(CONFIG_64BIT)
356*2d75891eSDaniel Golle # define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32)
357*2d75891eSDaniel Golle # define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32))
358*2d75891eSDaniel Golle #else
359*2d75891eSDaniel Golle # define RX_DMA_GET_ADDR64(x) (0)
360*2d75891eSDaniel Golle # define RX_DMA_PREP_ADDR64(x) (0)
361*2d75891eSDaniel Golle #endif
362656e7052SJohn Crispin
363656e7052SJohn Crispin /* QDMA descriptor rxd3 */
364160d3a9bSLorenzo Bianconi #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK)
365160d3a9bSLorenzo Bianconi #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
366160d3a9bSLorenzo Bianconi #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff)
367656e7052SJohn Crispin
368656e7052SJohn Crispin /* QDMA descriptor rxd4 */
369ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
370ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
371ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19)
372ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22)
373ba37b7caSFelix Fietkau
374ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */
375656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24)
376296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
377d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22)
378656e7052SJohn Crispin
3790cf731f9SLorenzo Bianconi /* PDMA descriptor rxd5 */
3800cf731f9SLorenzo Bianconi #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0)
3810cf731f9SLorenzo Bianconi #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18)
3820cf731f9SLorenzo Bianconi #define MTK_RXD5_SRC_PORT GENMASK(29, 26)
3830cf731f9SLorenzo Bianconi
384c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7)
385c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf)
386160d3a9bSLorenzo Bianconi
387160d3a9bSLorenzo Bianconi /* PDMA V2 descriptor rxd3 */
388160d3a9bSLorenzo Bianconi #define RX_DMA_VTAG_V2 BIT(0)
389160d3a9bSLorenzo Bianconi #define RX_DMA_L4_VALID_V2 BIT(2)
390160d3a9bSLorenzo Bianconi
391c0a44003SDaniel Golle /* PHY Polling and SMI Master Control registers */
392c0a44003SDaniel Golle #define MTK_PPSC 0x10000
393c0a44003SDaniel Golle #define PPSC_MDC_CFG GENMASK(29, 24)
394c0a44003SDaniel Golle #define PPSC_MDC_TURBO BIT(20)
395c0a44003SDaniel Golle #define MDC_MAX_FREQ 25000000
396c0a44003SDaniel Golle #define MDC_MAX_DIVIDER 63
397c0a44003SDaniel Golle
398656e7052SJohn Crispin /* PHY Indirect Access Control registers */
399656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004
400656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31)
401eda80b24SDaniel Golle #define PHY_IAC_REG_MASK GENMASK(29, 25)
402eda80b24SDaniel Golle #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x))
403eda80b24SDaniel Golle #define PHY_IAC_ADDR_MASK GENMASK(24, 20)
404eda80b24SDaniel Golle #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
405eda80b24SDaniel Golle #define PHY_IAC_CMD_MASK GENMASK(19, 18)
406e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
407eda80b24SDaniel Golle #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
408eda80b24SDaniel Golle #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
409e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
410eda80b24SDaniel Golle #define PHY_IAC_START_MASK GENMASK(17, 16)
411e2e7f6e2SDaniel Golle #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
412eda80b24SDaniel Golle #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
413eda80b24SDaniel Golle #define PHY_IAC_DATA_MASK GENMASK(15, 0)
414eda80b24SDaniel Golle #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
415656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ
416656e7052SJohn Crispin
41742c03844SSean Wang #define MTK_MAC_MISC 0x1000c
418445eb644SLorenzo Bianconi #define MTK_MAC_MISC_V3 0x10010
41942c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0)
420445eb644SLorenzo Bianconi #define MISC_MDC_TURBO BIT(4)
421445eb644SLorenzo Bianconi
422445eb644SLorenzo Bianconi /* XMAC status registers */
423445eb644SLorenzo Bianconi #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
424445eb644SLorenzo Bianconi #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
425445eb644SLorenzo Bianconi #define MTK_USXGMII_PCS_LINK BIT(8)
426445eb644SLorenzo Bianconi #define MTK_XGMAC_RX_FC BIT(5)
427445eb644SLorenzo Bianconi #define MTK_XGMAC_TX_FC BIT(4)
428445eb644SLorenzo Bianconi #define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
429445eb644SLorenzo Bianconi #define MTK_XGMAC_LINK_STS BIT(0)
430445eb644SLorenzo Bianconi
431445eb644SLorenzo Bianconi /* GSW bridge registers */
432445eb644SLorenzo Bianconi #define MTK_GSW_CFG (0x10080)
433445eb644SLorenzo Bianconi #define GSWTX_IPG_MASK GENMASK(19, 16)
434445eb644SLorenzo Bianconi #define GSWTX_IPG_SHIFT 16
435445eb644SLorenzo Bianconi #define GSWRX_IPG_MASK GENMASK(3, 0)
436445eb644SLorenzo Bianconi #define GSWRX_IPG_SHIFT 0
437445eb644SLorenzo Bianconi #define GSW_IPG_11 11
43842c03844SSean Wang
439656e7052SJohn Crispin /* Mac control registers */
440656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
4414fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24)
4424fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24))
4434fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0
4444fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1
4454fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2
4464fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3
447656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
448656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15)
449656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14)
450656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13)
451193250acSDaniel Golle #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12)
452656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9)
453656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8)
454656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5)
455656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4)
456656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3)
457656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2)
458656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1)
459656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0)
460b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
461b8fc9f30SRené van Dorst
462b8fc9f30SRené van Dorst /* Mac status registers */
463b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
464b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7)
465b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6)
466b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5)
467b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4)
468b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3)
469b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2)
470b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
471b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1)
472b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0)
473656e7052SJohn Crispin
474f430dea7SSean Wang /* TRGMII RXC control register */
475f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300
476f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
477f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8))
478f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
479a5d75538SRené van Dorst #define RXC_RST BIT(31)
480f430dea7SSean Wang #define RXC_DQSISEL BIT(30)
481f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
482f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
483f430dea7SSean Wang
484a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5
485a5d75538SRené van Dorst
486f430dea7SSean Wang /* TRGMII RXC control register */
487f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340
488f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
489f430dea7SSean Wang #define TXC_INV BIT(30)
490f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
491f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
492f430dea7SSean Wang
493a5d75538SRené van Dorst /* TRGMII TX Drive Strength */
494a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
495a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf)
496a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
497a5d75538SRené van Dorst
498f430dea7SSean Wang /* TRGMII Interface mode register */
499f430dea7SSean Wang #define INTF_MODE 0x10390
500f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0)
501f430dea7SSean Wang #define TRGMII_MODE BIT(1)
502f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2)
503f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
504f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0
505f430dea7SSean Wang
506656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/
507656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0
508656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0
509656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00
510656e7052SJohn Crispin
511b95b6d99SNelson Chang /* ethernet subsystem chip id register */
512b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0
513b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4
514983e1a6cSNelson Chang #define MT7623_ETH 7623
51542c03844SSean Wang #define MT7622_ETH 7622
516889bcbdeSBjørn Mork #define MT7621_ETH 7621
517b95b6d99SNelson Chang
5188efaa653SRené van Dorst /* ethernet system control register */
5198efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10
5208efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
5218efaa653SRené van Dorst
522656e7052SJohn Crispin /* ethernet subsystem config register */
523656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14
524656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3
525656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
526cfb5677dSDaniel Golle #define SYSCFG0_SGMII_MASK GENMASK(9, 7)
5277093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
5287093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
5297093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
5307093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
5317093f9d8SSean Wang
532656e7052SJohn Crispin
533f430dea7SSean Wang /* ethernet subsystem clock register */
534f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c
535f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
5368efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
5378efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6)
5388efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
539f430dea7SSean Wang
5402a8307aaSSean Wang /* ethernet reset control register */
5412a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34
5422a8307aaSSean Wang #define RSTCTRL_FE BIT(6)
54388c1e6efSDaniel Golle #define RSTCTRL_WDMA0 BIT(24)
54488c1e6efSDaniel Golle #define RSTCTRL_WDMA1 BIT(25)
54588c1e6efSDaniel Golle #define RSTCTRL_WDMA2 BIT(26)
546ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0 BIT(31)
547ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0_V2 BIT(30)
548ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE1 BIT(31)
54988c1e6efSDaniel Golle #define RSTCTRL_PPE0_V3 BIT(29)
55088c1e6efSDaniel Golle #define RSTCTRL_PPE1_V3 BIT(30)
55188c1e6efSDaniel Golle #define RSTCTRL_PPE2 BIT(31)
552160d3a9bSLorenzo Bianconi #define RSTCTRL_ETH BIT(23)
553160d3a9bSLorenzo Bianconi
554160d3a9bSLorenzo Bianconi /* ethernet reset check idle register */
555160d3a9bSLorenzo Bianconi #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
556160d3a9bSLorenzo Bianconi
557d776a57eSFelix Fietkau /* ethernet dma channel agent map */
558d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP 0x408
559d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
560d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
561d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
562d776a57eSFelix Fietkau
5637093f9d8SSean Wang /* Infrasys subsystem config registers */
5647093f9d8SSean Wang #define INFRA_MISC2 0x70c
5657093f9d8SSean Wang #define CO_QPHY_SEL BIT(0)
5667093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1)
5677093f9d8SSean Wang
568f5d43dddSDaniel Golle /* Top misc registers */
569f5d43dddSDaniel Golle #define USB_PHY_SWITCH_REG 0x218
570f5d43dddSDaniel Golle #define QPHY_SEL_MASK GENMASK(1, 0)
571f5d43dddSDaniel Golle #define SGMII_QPHY_SEL 0x2
572f5d43dddSDaniel Golle
573296c9120SStefan Roese /* MT7628/88 specific stuff */
574296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800
575296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00
576296c9120SStefan Roese
577296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
578296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
579296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
580296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
581296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0)
582296c9120SStefan Roese
583296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
584296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
585296c9120SStefan Roese
586ad79fd2cSStefan Roese /* Counter / stat register */
587ad79fd2cSStefan Roese #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
588ad79fd2cSStefan Roese #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
589ad79fd2cSStefan Roese #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
590ad79fd2cSStefan Roese #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
591ad79fd2cSStefan Roese #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
592ad79fd2cSStefan Roese
59393b2591aSLorenzo Bianconi #define MTK_FE_CDM1_FSM 0x220
59493b2591aSLorenzo Bianconi #define MTK_FE_CDM2_FSM 0x224
59593b2591aSLorenzo Bianconi #define MTK_FE_CDM3_FSM 0x238
59693b2591aSLorenzo Bianconi #define MTK_FE_CDM4_FSM 0x298
59793b2591aSLorenzo Bianconi #define MTK_FE_CDM5_FSM 0x318
59893b2591aSLorenzo Bianconi #define MTK_FE_CDM6_FSM 0x328
59993b2591aSLorenzo Bianconi #define MTK_FE_GDM1_FSM 0x228
60093b2591aSLorenzo Bianconi #define MTK_FE_GDM2_FSM 0x22C
60193b2591aSLorenzo Bianconi
60293b2591aSLorenzo Bianconi #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
60393b2591aSLorenzo Bianconi
604656e7052SJohn Crispin struct mtk_rx_dma {
605656e7052SJohn Crispin unsigned int rxd1;
606656e7052SJohn Crispin unsigned int rxd2;
607656e7052SJohn Crispin unsigned int rxd3;
608656e7052SJohn Crispin unsigned int rxd4;
609656e7052SJohn Crispin } __packed __aligned(4);
610656e7052SJohn Crispin
611160d3a9bSLorenzo Bianconi struct mtk_rx_dma_v2 {
612160d3a9bSLorenzo Bianconi unsigned int rxd1;
613160d3a9bSLorenzo Bianconi unsigned int rxd2;
614160d3a9bSLorenzo Bianconi unsigned int rxd3;
615160d3a9bSLorenzo Bianconi unsigned int rxd4;
616160d3a9bSLorenzo Bianconi unsigned int rxd5;
617160d3a9bSLorenzo Bianconi unsigned int rxd6;
618160d3a9bSLorenzo Bianconi unsigned int rxd7;
619160d3a9bSLorenzo Bianconi unsigned int rxd8;
620160d3a9bSLorenzo Bianconi } __packed __aligned(4);
621160d3a9bSLorenzo Bianconi
622656e7052SJohn Crispin struct mtk_tx_dma {
623656e7052SJohn Crispin unsigned int txd1;
624656e7052SJohn Crispin unsigned int txd2;
625656e7052SJohn Crispin unsigned int txd3;
626656e7052SJohn Crispin unsigned int txd4;
627656e7052SJohn Crispin } __packed __aligned(4);
628656e7052SJohn Crispin
629160d3a9bSLorenzo Bianconi struct mtk_tx_dma_v2 {
630160d3a9bSLorenzo Bianconi unsigned int txd1;
631160d3a9bSLorenzo Bianconi unsigned int txd2;
632160d3a9bSLorenzo Bianconi unsigned int txd3;
633160d3a9bSLorenzo Bianconi unsigned int txd4;
634160d3a9bSLorenzo Bianconi unsigned int txd5;
635160d3a9bSLorenzo Bianconi unsigned int txd6;
636160d3a9bSLorenzo Bianconi unsigned int txd7;
637160d3a9bSLorenzo Bianconi unsigned int txd8;
638160d3a9bSLorenzo Bianconi } __packed __aligned(4);
639160d3a9bSLorenzo Bianconi
640656e7052SJohn Crispin struct mtk_eth;
641656e7052SJohn Crispin struct mtk_mac;
642656e7052SJohn Crispin
643916a6ee8SLorenzo Bianconi struct mtk_xdp_stats {
644916a6ee8SLorenzo Bianconi u64 rx_xdp_redirect;
645916a6ee8SLorenzo Bianconi u64 rx_xdp_pass;
646916a6ee8SLorenzo Bianconi u64 rx_xdp_drop;
647916a6ee8SLorenzo Bianconi u64 rx_xdp_tx;
648916a6ee8SLorenzo Bianconi u64 rx_xdp_tx_errors;
649916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit;
650916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit_errors;
651916a6ee8SLorenzo Bianconi };
652916a6ee8SLorenzo Bianconi
653656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics.
654656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic
655656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC
656656e7052SJohn Crispin * @syncp: the refcount
657656e7052SJohn Crispin *
658656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics.
659656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these
660656e7052SJohn Crispin * counters and store them in this struct.
661656e7052SJohn Crispin */
662656e7052SJohn Crispin struct mtk_hw_stats {
663656e7052SJohn Crispin u64 tx_bytes;
664656e7052SJohn Crispin u64 tx_packets;
665656e7052SJohn Crispin u64 tx_skip;
666656e7052SJohn Crispin u64 tx_collisions;
667656e7052SJohn Crispin u64 rx_bytes;
668656e7052SJohn Crispin u64 rx_packets;
669656e7052SJohn Crispin u64 rx_overflow;
670656e7052SJohn Crispin u64 rx_fcs_errors;
671656e7052SJohn Crispin u64 rx_short_errors;
672656e7052SJohn Crispin u64 rx_long_errors;
673656e7052SJohn Crispin u64 rx_checksum_errors;
674656e7052SJohn Crispin u64 rx_flow_control_packets;
675656e7052SJohn Crispin
676916a6ee8SLorenzo Bianconi struct mtk_xdp_stats xdp_stats;
677916a6ee8SLorenzo Bianconi
678656e7052SJohn Crispin spinlock_t stats_lock;
679656e7052SJohn Crispin u32 reg_offset;
680656e7052SJohn Crispin struct u64_stats_sync syncp;
681656e7052SJohn Crispin };
682656e7052SJohn Crispin
683656e7052SJohn Crispin enum mtk_tx_flags {
684134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to
685134d2152SSean Wang * track how memory was allocated so that it can be freed properly.
686134d2152SSean Wang */
687656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01,
688656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02,
689656e7052SJohn Crispin };
690656e7052SJohn Crispin
691549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the
692549e5495SSean Wang * clock in the order
693549e5495SSean Wang */
694549e5495SSean Wang enum mtk_clks_map {
695549e5495SSean Wang MTK_CLK_ETHIF,
696d438e298SSean Wang MTK_CLK_SGMIITOP,
697549e5495SSean Wang MTK_CLK_ESW,
69842c03844SSean Wang MTK_CLK_GP0,
699549e5495SSean Wang MTK_CLK_GP1,
700549e5495SSean Wang MTK_CLK_GP2,
701445eb644SLorenzo Bianconi MTK_CLK_GP3,
702445eb644SLorenzo Bianconi MTK_CLK_XGP1,
703445eb644SLorenzo Bianconi MTK_CLK_XGP2,
704445eb644SLorenzo Bianconi MTK_CLK_XGP3,
705445eb644SLorenzo Bianconi MTK_CLK_CRYPTO,
706d438e298SSean Wang MTK_CLK_FE,
707f430dea7SSean Wang MTK_CLK_TRGPLL,
70842c03844SSean Wang MTK_CLK_SGMII_TX_250M,
70942c03844SSean Wang MTK_CLK_SGMII_RX_250M,
71042c03844SSean Wang MTK_CLK_SGMII_CDR_REF,
71142c03844SSean Wang MTK_CLK_SGMII_CDR_FB,
712d438e298SSean Wang MTK_CLK_SGMII2_TX_250M,
713d438e298SSean Wang MTK_CLK_SGMII2_RX_250M,
714d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF,
715d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB,
71642c03844SSean Wang MTK_CLK_SGMII_CK,
71742c03844SSean Wang MTK_CLK_ETH2PLL,
718197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU0,
719197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU1,
720197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS0,
721197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS1,
722445eb644SLorenzo Bianconi MTK_CLK_ETHWARP_WOCPU2,
723445eb644SLorenzo Bianconi MTK_CLK_ETHWARP_WOCPU1,
724445eb644SLorenzo Bianconi MTK_CLK_ETHWARP_WOCPU0,
725445eb644SLorenzo Bianconi MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
726445eb644SLorenzo Bianconi MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
727445eb644SLorenzo Bianconi MTK_CLK_TOP_SGM_0_SEL,
728445eb644SLorenzo Bianconi MTK_CLK_TOP_SGM_1_SEL,
729445eb644SLorenzo Bianconi MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
730445eb644SLorenzo Bianconi MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
731445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_GMII_SEL,
732445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_REFCK_50M_SEL,
733445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_SYS_200M_SEL,
734445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_SYS_SEL,
735445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_XGMII_SEL,
736445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_MII_SEL,
737445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_SEL,
738445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_500M_SEL,
739445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
740445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
741445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
742445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_WARP_SEL,
743549e5495SSean Wang MTK_CLK_MAX
744549e5495SSean Wang };
745549e5495SSean Wang
746c75e416cSDaniel Golle #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
747c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
748c75e416cSDaniel Golle BIT_ULL(MTK_CLK_TRGPLL))
749c75e416cSDaniel Golle #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
750c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
751c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP2) | \
752c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
753c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
754c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
755c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
756c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CK) | \
757c75e416cSDaniel Golle BIT_ULL(MTK_CLK_ETH2PLL))
758889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0)
759296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0)
760c75e416cSDaniel Golle #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
761c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
762c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
763c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
764c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
765c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
766c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
767c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
768c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
769c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
770c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
771c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CK) | \
772c75e416cSDaniel Golle BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
773c75e416cSDaniel Golle #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
774c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP1) | \
775c75e416cSDaniel Golle BIT_ULL(MTK_CLK_WOCPU0) | \
776c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
777c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
778c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
779c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
780c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
781c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
782c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
783c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
784c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CK))
785c75e416cSDaniel Golle #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
786c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP1) | \
787c75e416cSDaniel Golle BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
788c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
789c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
790c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
791c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
792c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
793c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
794c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
795c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
796445eb644SLorenzo Bianconi #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
797445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
798445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
799445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
800445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_CRYPTO) | \
801445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
802445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
803445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
804445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
805445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
806445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
807445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
808445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
809445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
810445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
811445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
812445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
813445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
814445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
815445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
816445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
817445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
818445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
819445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
820445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
821445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
822445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
823445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
824445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
825445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
826889bcbdeSBjørn Mork
8279ea4d311SSean Wang enum mtk_dev_state {
828dce6fa42SSean Wang MTK_HW_INIT,
829dce6fa42SSean Wang MTK_RESETTING
8309ea4d311SSean Wang };
8319ea4d311SSean Wang
8321953f134SLorenzo Bianconi /* PSE Port Definition */
8331953f134SLorenzo Bianconi enum mtk_pse_port {
8341953f134SLorenzo Bianconi PSE_ADMA_PORT = 0,
8351953f134SLorenzo Bianconi PSE_GDM1_PORT,
8361953f134SLorenzo Bianconi PSE_GDM2_PORT,
8371953f134SLorenzo Bianconi PSE_PPE0_PORT,
8381953f134SLorenzo Bianconi PSE_PPE1_PORT,
8391953f134SLorenzo Bianconi PSE_QDMA_TX_PORT,
8401953f134SLorenzo Bianconi PSE_QDMA_RX_PORT,
8411953f134SLorenzo Bianconi PSE_DROP_PORT,
8421953f134SLorenzo Bianconi PSE_WDMA0_PORT,
8431953f134SLorenzo Bianconi PSE_WDMA1_PORT,
8441953f134SLorenzo Bianconi PSE_TDMA_PORT,
8451953f134SLorenzo Bianconi PSE_NONE_PORT,
8461953f134SLorenzo Bianconi PSE_PPE2_PORT,
8471953f134SLorenzo Bianconi PSE_WDMA2_PORT,
8481953f134SLorenzo Bianconi PSE_EIP197_PORT,
8491953f134SLorenzo Bianconi PSE_GDM3_PORT,
8501953f134SLorenzo Bianconi PSE_PORT_MAX
8511953f134SLorenzo Bianconi };
8521953f134SLorenzo Bianconi
8531953f134SLorenzo Bianconi /* GMAC Identifier */
8541953f134SLorenzo Bianconi enum mtk_gmac_id {
8551953f134SLorenzo Bianconi MTK_GMAC1_ID = 0,
8561953f134SLorenzo Bianconi MTK_GMAC2_ID,
8571953f134SLorenzo Bianconi MTK_GMAC3_ID,
8581953f134SLorenzo Bianconi MTK_GMAC_ID_MAX
8591953f134SLorenzo Bianconi };
8601953f134SLorenzo Bianconi
8615886d26fSLorenzo Bianconi enum mtk_tx_buf_type {
8625886d26fSLorenzo Bianconi MTK_TYPE_SKB,
8635886d26fSLorenzo Bianconi MTK_TYPE_XDP_TX,
8645886d26fSLorenzo Bianconi MTK_TYPE_XDP_NDO,
8655886d26fSLorenzo Bianconi };
8665886d26fSLorenzo Bianconi
867656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
868656e7052SJohn Crispin * by the TX descriptor s
869656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent
870656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment
871656e7052SJohn Crispin * @dma_len0: The length of the first segment
872656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment
873656e7052SJohn Crispin * @dma_len1: The length of the second segment
874656e7052SJohn Crispin */
875656e7052SJohn Crispin struct mtk_tx_buf {
8765886d26fSLorenzo Bianconi enum mtk_tx_buf_type type;
8775886d26fSLorenzo Bianconi void *data;
8785886d26fSLorenzo Bianconi
8791953f134SLorenzo Bianconi u16 mac_id;
8801953f134SLorenzo Bianconi u16 flags;
881656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0);
882656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0);
883656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1);
884656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1);
885656e7052SJohn Crispin };
886656e7052SJohn Crispin
887656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring
888656e7052SJohn Crispin * @dma: The descriptor ring
889656e7052SJohn Crispin * @buf: The memory pointed at by the ring
890656e7052SJohn Crispin * @phys: The physical addr of tx_buf
891656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor
892656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor
8934e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor
894656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors
895656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors
896656e7052SJohn Crispin * are present
897656e7052SJohn Crispin */
898656e7052SJohn Crispin struct mtk_tx_ring {
8997173eca8SLorenzo Bianconi void *dma;
900656e7052SJohn Crispin struct mtk_tx_buf *buf;
901656e7052SJohn Crispin dma_addr_t phys;
902656e7052SJohn Crispin struct mtk_tx_dma *next_free;
903656e7052SJohn Crispin struct mtk_tx_dma *last_free;
9044e6bf609SFelix Fietkau u32 last_free_ptr;
905656e7052SJohn Crispin u16 thresh;
906656e7052SJohn Crispin atomic_t free_count;
907296c9120SStefan Roese int dma_size;
908296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
909296c9120SStefan Roese dma_addr_t phys_pdma;
910296c9120SStefan Roese int cpu_idx;
911656e7052SJohn Crispin };
912656e7052SJohn Crispin
913ee406810SNelson Chang /* PDMA rx ring mode */
914ee406810SNelson Chang enum mtk_rx_flags {
915ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0,
916ee406810SNelson Chang MTK_RX_FLAGS_HWLRO,
9176427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA,
918ee406810SNelson Chang };
919ee406810SNelson Chang
920656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring
921656e7052SJohn Crispin * @dma: The descriptor ring
922656e7052SJohn Crispin * @data: The memory pointed at by the ring
923656e7052SJohn Crispin * @phys: The physical addr of rx_buf
924656e7052SJohn Crispin * @frag_size: How big can each fragment be
925656e7052SJohn Crispin * @buf_size: The size of each packet buffer
926656e7052SJohn Crispin * @calc_idx: The current head of ring
927656e7052SJohn Crispin */
928656e7052SJohn Crispin struct mtk_rx_ring {
9297173eca8SLorenzo Bianconi void *dma;
930656e7052SJohn Crispin u8 **data;
931656e7052SJohn Crispin dma_addr_t phys;
932656e7052SJohn Crispin u16 frag_size;
933656e7052SJohn Crispin u16 buf_size;
934ee406810SNelson Chang u16 dma_size;
935ee406810SNelson Chang bool calc_idx_update;
936656e7052SJohn Crispin u16 calc_idx;
937ee406810SNelson Chang u32 crx_idx_reg;
93823233e57SLorenzo Bianconi /* page_pool */
93923233e57SLorenzo Bianconi struct page_pool *page_pool;
94023233e57SLorenzo Bianconi struct xdp_rxq_info xdp_q;
941656e7052SJohn Crispin };
942656e7052SJohn Crispin
943e2c74694SRené van Dorst enum mkt_eth_capabilities {
944e2c74694SRené van Dorst MTK_RGMII_BIT = 0,
945e2c74694SRené van Dorst MTK_TRGMII_BIT,
946e2c74694SRené van Dorst MTK_SGMII_BIT,
947e2c74694SRené van Dorst MTK_ESW_BIT,
948e2c74694SRené van Dorst MTK_GEPHY_BIT,
949e2c74694SRené van Dorst MTK_MUX_BIT,
950e2c74694SRené van Dorst MTK_INFRA_BIT,
951e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT,
952e2c74694SRené van Dorst MTK_HWLRO_BIT,
953e2c74694SRené van Dorst MTK_SHARED_INT_BIT,
954e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT,
955296c9120SStefan Roese MTK_QDMA_BIT,
956296c9120SStefan Roese MTK_SOC_MT7628_BIT,
957160d3a9bSLorenzo Bianconi MTK_RSTCTRL_PPE1_BIT,
95888c1e6efSDaniel Golle MTK_RSTCTRL_PPE2_BIT,
959f5d43dddSDaniel Golle MTK_U3_COPHY_V2_BIT,
960ebb1e4f9SDaniel Golle MTK_SRAM_BIT,
961*2d75891eSDaniel Golle MTK_36BIT_DMA_BIT,
9627093f9d8SSean Wang
963e2c74694SRené van Dorst /* MUX BITS*/
964e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
965e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
966e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
967e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
968e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
969e2c74694SRené van Dorst
970e2c74694SRené van Dorst /* PATH BITS */
971e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT,
972e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT,
973e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT,
974e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT,
975e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT,
976e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT,
977e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT,
9787093f9d8SSean Wang };
9797093f9d8SSean Wang
9807093f9d8SSean Wang /* Supported hardware group on SoCs */
98151a4df60SLorenzo Bianconi #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
98251a4df60SLorenzo Bianconi #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
98351a4df60SLorenzo Bianconi #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
98451a4df60SLorenzo Bianconi #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
98551a4df60SLorenzo Bianconi #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
98651a4df60SLorenzo Bianconi #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
98751a4df60SLorenzo Bianconi #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT)
98851a4df60SLorenzo Bianconi #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT)
98951a4df60SLorenzo Bianconi #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT)
99051a4df60SLorenzo Bianconi #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT)
99151a4df60SLorenzo Bianconi #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
99251a4df60SLorenzo Bianconi #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT)
99351a4df60SLorenzo Bianconi #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT)
99451a4df60SLorenzo Bianconi #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
99588c1e6efSDaniel Golle #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
99651a4df60SLorenzo Bianconi #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
997ebb1e4f9SDaniel Golle #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
998*2d75891eSDaniel Golle #define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
999e2c74694SRené van Dorst
1000e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
100151a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
1002e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
100351a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
1004e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
100551a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
1006e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
100751a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
1008e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
100951a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
10107093f9d8SSean Wang
10117093f9d8SSean Wang /* Supported path present on SoCs */
101251a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
101351a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
101451a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
101551a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
101651a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
101751a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
101851a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
10197093f9d8SSean Wang
1020e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
1021e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
1022e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
1023e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
1024e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
1025e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
1026e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
10277093f9d8SSean Wang
10287093f9d8SSean Wang /* MUXes present on SoCs */
10297093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
1030e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
10317093f9d8SSean Wang
10327093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
10337093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
1034e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
10357093f9d8SSean Wang
10367093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
10377093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \
1038e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
10397093f9d8SSean Wang
10407093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
10417093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1042e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
10437093f9d8SSean Wang MTK_SHARED_SGMII)
10447093f9d8SSean Wang
10457093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
10467093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
1047e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
10487093f9d8SSean Wang
10492ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
10502ec50f57SSean Wang
10518efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
1052296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \
1053296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA)
10548efaa653SRené van Dorst
10557093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
10567093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
10577093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \
1058296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
10597093f9d8SSean Wang
1060296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
1061296c9120SStefan Roese MTK_QDMA)
1062296c9120SStefan Roese
1063296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
10647093f9d8SSean Wang
10657093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
10667093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
10677093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
10687093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \
1069296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
10707093f9d8SSean Wang
1071f5d43dddSDaniel Golle #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1072f5d43dddSDaniel Golle MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1073f5d43dddSDaniel Golle MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
1074ebb1e4f9SDaniel Golle MTK_RSTCTRL_PPE1 | MTK_SRAM)
1075f5d43dddSDaniel Golle
1076197c9e9bSLorenzo Bianconi #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
1077197c9e9bSLorenzo Bianconi MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1078ebb1e4f9SDaniel Golle MTK_RSTCTRL_PPE1 | MTK_SRAM)
1079197c9e9bSLorenzo Bianconi
1080*2d75891eSDaniel Golle #define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
1081*2d75891eSDaniel Golle MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
1082445eb644SLorenzo Bianconi
1083731f3fd6SLorenzo Bianconi struct mtk_tx_dma_desc_info {
1084731f3fd6SLorenzo Bianconi dma_addr_t addr;
1085731f3fd6SLorenzo Bianconi u32 size;
1086731f3fd6SLorenzo Bianconi u16 vlan_tci;
1087160d3a9bSLorenzo Bianconi u16 qid;
1088731f3fd6SLorenzo Bianconi u8 gso:1;
1089731f3fd6SLorenzo Bianconi u8 csum:1;
1090731f3fd6SLorenzo Bianconi u8 vlan:1;
1091731f3fd6SLorenzo Bianconi u8 first:1;
1092731f3fd6SLorenzo Bianconi u8 last:1;
1093731f3fd6SLorenzo Bianconi };
1094731f3fd6SLorenzo Bianconi
10958cb42714SLorenzo Bianconi struct mtk_reg_map {
10968cb42714SLorenzo Bianconi u32 tx_irq_mask;
10978cb42714SLorenzo Bianconi u32 tx_irq_status;
10988cb42714SLorenzo Bianconi struct {
10998cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */
11008cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */
11018cb42714SLorenzo Bianconi u32 pcrx_ptr; /* rx cpu pointer */
11028cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */
11038cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */
11048cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */
11058cb42714SLorenzo Bianconi u32 irq_status; /* interrupt status */
11068cb42714SLorenzo Bianconi u32 irq_mask; /* interrupt mask */
110793b2591aSLorenzo Bianconi u32 adma_rx_dbg0;
11088cb42714SLorenzo Bianconi u32 int_grp;
11098cb42714SLorenzo Bianconi } pdma;
11108cb42714SLorenzo Bianconi struct {
11118cb42714SLorenzo Bianconi u32 qtx_cfg; /* tx queue configuration */
1112f63959c7SFelix Fietkau u32 qtx_sch; /* tx queue scheduler configuration */
11138cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */
11148cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */
11158cb42714SLorenzo Bianconi u32 qcrx_ptr; /* rx cpu pointer */
11168cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */
11178cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */
11188cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */
11198cb42714SLorenzo Bianconi u32 fc_th; /* flow control */
11208cb42714SLorenzo Bianconi u32 int_grp;
11218cb42714SLorenzo Bianconi u32 hred; /* interrupt mask */
11228cb42714SLorenzo Bianconi u32 ctx_ptr; /* tx acquire cpu pointer */
11238cb42714SLorenzo Bianconi u32 dtx_ptr; /* tx acquire dma pointer */
11248cb42714SLorenzo Bianconi u32 crx_ptr; /* tx release cpu pointer */
11258cb42714SLorenzo Bianconi u32 drx_ptr; /* tx release dma pointer */
11268cb42714SLorenzo Bianconi u32 fq_head; /* fq head pointer */
11278cb42714SLorenzo Bianconi u32 fq_tail; /* fq tail pointer */
11288cb42714SLorenzo Bianconi u32 fq_count; /* fq free page count */
11298cb42714SLorenzo Bianconi u32 fq_blen; /* fq free page buffer length */
1130f63959c7SFelix Fietkau u32 tx_sch_rate; /* tx scheduler rate control registers */
11318cb42714SLorenzo Bianconi } qdma;
11328cb42714SLorenzo Bianconi u32 gdm1_cnt;
1133329bce51SLorenzo Bianconi u32 gdma_to_ppe;
1134329bce51SLorenzo Bianconi u32 ppe_base;
11350c1d3fb9SLorenzo Bianconi u32 wdma_base[2];
113693b2591aSLorenzo Bianconi u32 pse_iq_sta;
113793b2591aSLorenzo Bianconi u32 pse_oq_sta;
11388cb42714SLorenzo Bianconi };
11398cb42714SLorenzo Bianconi
114042c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences
11412ec50f57SSean Wang * among various plaforms
11428cb42714SLorenzo Bianconi * @reg_map Soc register map.
11439ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to
11449ffee4a8SSean Wang * sgmiisys syscon
11452ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC
1146296c9120SStefan Roese * @hw_features Flags shown HW features
11472ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on
11482ec50f57SSean Wang * the target SoC
1149243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires
1150243dc5fbSSean Wang * the extra setup for those pins used by GMAC.
1151ba2fc48cSLorenzo Bianconi * @hash_offset Flow table hash offset.
1152a008e2a8SLorenzo Bianconi * @version SoC version.
11539d8cb4c0SLorenzo Bianconi * @foe_entry_size Foe table entry size.
11543fbe4d8cSDaniel Golle * @has_accounting Bool indicating support for accounting of
11553fbe4d8cSDaniel Golle * offloaded flows.
1156eb067347SLorenzo Bianconi * @txd_size Tx DMA descriptor size.
1157670ff7daSLorenzo Bianconi * @rxd_size Rx DMA descriptor size.
1158160d3a9bSLorenzo Bianconi * @rx_irq_done_mask Rx irq done register mask.
1159160d3a9bSLorenzo Bianconi * @rx_dma_l4_valid Rx DMA valid register mask.
1160160d3a9bSLorenzo Bianconi * @dma_max_len Max DMA tx/rx buffer length.
1161160d3a9bSLorenzo Bianconi * @dma_len_offset Tx/Rx DMA length field offset.
11622ec50f57SSean Wang */
11632ec50f57SSean Wang struct mtk_soc_data {
11648cb42714SLorenzo Bianconi const struct mtk_reg_map *reg_map;
11659ffee4a8SSean Wang u32 ana_rgc3;
116651a4df60SLorenzo Bianconi u64 caps;
1167c75e416cSDaniel Golle u64 required_clks;
1168243dc5fbSSean Wang bool required_pctl;
1169ba37b7caSFelix Fietkau u8 offload_version;
1170ba2fc48cSLorenzo Bianconi u8 hash_offset;
1171a008e2a8SLorenzo Bianconi u8 version;
11729d8cb4c0SLorenzo Bianconi u16 foe_entry_size;
1173296c9120SStefan Roese netdev_features_t hw_features;
11743fbe4d8cSDaniel Golle bool has_accounting;
117576a4cb75SRussell King (Oracle) bool disable_pll_modes;
1176eb067347SLorenzo Bianconi struct {
1177eb067347SLorenzo Bianconi u32 txd_size;
1178670ff7daSLorenzo Bianconi u32 rxd_size;
1179160d3a9bSLorenzo Bianconi u32 rx_irq_done_mask;
1180160d3a9bSLorenzo Bianconi u32 rx_dma_l4_valid;
1181160d3a9bSLorenzo Bianconi u32 dma_max_len;
1182160d3a9bSLorenzo Bianconi u32 dma_len_offset;
1183eb067347SLorenzo Bianconi } txrx;
11842ec50f57SSean Wang };
11852ec50f57SSean Wang
118693b2591aSLorenzo Bianconi #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
118793b2591aSLorenzo Bianconi
11886ca26557SLorenzo Bianconi /* currently no SoC has more than 3 macs */
11896ca26557SLorenzo Bianconi #define MTK_MAX_DEVS 3
1190656e7052SJohn Crispin
1191656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state
1192656e7052SJohn Crispin * of the driver
1193656e7052SJohn Crispin * @dev: The device pointer
1194d776a57eSFelix Fietkau * @dev: The device pointer used for dma mapping/alloc
1195656e7052SJohn Crispin * @base: The mapped register i/o base
1196656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic
11975cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic
11985cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic
1199e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic
1200656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
1201656e7052SJohn Crispin * dummy for NAPI to work
1202656e7052SJohn Crispin * @netdev: The netdev instances
1203656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC
1204656e7052SJohn Crispin * @irq: The IRQ that we are using
1205656e7052SJohn Crispin * @msg_enable: Ethtool msg level
1206656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup
1207656e7052SJohn Crispin * MII modes
12087093f9d8SSean Wang * @infra: The register map pointing at the range used to setup
12097093f9d8SSean Wang * SGMII and GePHY path
12102a3ec7aeSDaniel Golle * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
1211656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup
1212656e7052SJohn Crispin * GMAC port drive/slew values
1213656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine
12140c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring
12150c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring
12166427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
121780673029SJohn Crispin * @tx_napi: The TX NAPI struct
121880673029SJohn Crispin * @rx_napi: The RX NAPI struct
1219e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter
1220e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter
1221e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter
1222e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context
1223e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter
1224e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter
1225e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter
1226e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context
1227656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
1228605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring
1229656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to.
1230549e5495SSean Wang * @clks: clock array for all clocks required
1231656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it
12327c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring
123342c03844SSean Wang * @state: Initialization and runtime state of the device
12342ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs
1235656e7052SJohn Crispin */
1236656e7052SJohn Crispin
1237656e7052SJohn Crispin struct mtk_eth {
1238656e7052SJohn Crispin struct device *dev;
1239d776a57eSFelix Fietkau struct device *dma_dev;
1240656e7052SJohn Crispin void __iomem *base;
1241ebb1e4f9SDaniel Golle void *sram_base;
1242656e7052SJohn Crispin spinlock_t page_lock;
12435cce0322SJohn Crispin spinlock_t tx_irq_lock;
12445cce0322SJohn Crispin spinlock_t rx_irq_lock;
1245656e7052SJohn Crispin struct net_device dummy_dev;
1246656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS];
1247656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS];
124880673029SJohn Crispin int irq[3];
1249656e7052SJohn Crispin u32 msg_enable;
1250656e7052SJohn Crispin unsigned long sysclk;
1251656e7052SJohn Crispin struct regmap *ethsys;
12527093f9d8SSean Wang struct regmap *infra;
12532a3ec7aeSDaniel Golle struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
1254656e7052SJohn Crispin struct regmap *pctl;
1255ee406810SNelson Chang bool hwlro;
1256c6d4e63eSElena Reshetova refcount_t dma_refcnt;
1257656e7052SJohn Crispin struct mtk_tx_ring tx_ring;
1258ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
12596427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma;
126080673029SJohn Crispin struct napi_struct tx_napi;
1261656e7052SJohn Crispin struct napi_struct rx_napi;
12624d642690SLorenzo Bianconi void *scratch_ring;
1263605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring;
1264656e7052SJohn Crispin void *scratch_head;
1265549e5495SSean Wang struct clk *clks[MTK_CLK_MAX];
1266549e5495SSean Wang
1267656e7052SJohn Crispin struct mii_bus *mii_bus;
12687c78b4adSJohn Crispin struct work_struct pending_work;
12699ea4d311SSean Wang unsigned long state;
12702ec50f57SSean Wang
12712ec50f57SSean Wang const struct mtk_soc_data *soc;
1272296c9120SStefan Roese
1273e9229ffdSFelix Fietkau spinlock_t dim_lock;
1274e9229ffdSFelix Fietkau
1275e9229ffdSFelix Fietkau u32 rx_events;
1276e9229ffdSFelix Fietkau u32 rx_packets;
1277e9229ffdSFelix Fietkau u32 rx_bytes;
1278e9229ffdSFelix Fietkau struct dim rx_dim;
1279e9229ffdSFelix Fietkau
1280e9229ffdSFelix Fietkau u32 tx_events;
1281e9229ffdSFelix Fietkau u32 tx_packets;
1282e9229ffdSFelix Fietkau u32 tx_bytes;
1283e9229ffdSFelix Fietkau struct dim tx_dim;
1284e9229ffdSFelix Fietkau
1285296c9120SStefan Roese int ip_align;
1286ba37b7caSFelix Fietkau
12872d7605a7SFelix Fietkau struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS];
12882d7605a7SFelix Fietkau
12894ff1a3fcSLorenzo Bianconi struct mtk_ppe *ppe[2];
1290502e84e2SFelix Fietkau struct rhashtable flow_table;
12917c26c20dSLorenzo Bianconi
12927c26c20dSLorenzo Bianconi struct bpf_prog __rcu *prog;
129393b2591aSLorenzo Bianconi
129493b2591aSLorenzo Bianconi struct {
129593b2591aSLorenzo Bianconi struct delayed_work monitor_work;
129693b2591aSLorenzo Bianconi u32 wdidx;
129793b2591aSLorenzo Bianconi u8 wdma_hang_count;
129893b2591aSLorenzo Bianconi u8 qdma_hang_count;
129993b2591aSLorenzo Bianconi u8 adma_hang_count;
130093b2591aSLorenzo Bianconi } reset;
1301656e7052SJohn Crispin };
1302656e7052SJohn Crispin
1303656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the
1304656e7052SJohn Crispin * SoC
1305656e7052SJohn Crispin * @id: The number of the MAC
1306b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings
1307656e7052SJohn Crispin * @of_node: Our devicetree node
1308656e7052SJohn Crispin * @hw: Backpointer to our main datastruture
1309656e7052SJohn Crispin * @hw_stats: Packet statistics counter
1310656e7052SJohn Crispin */
1311656e7052SJohn Crispin struct mtk_mac {
1312656e7052SJohn Crispin int id;
1313b8fc9f30SRené van Dorst phy_interface_t interface;
1314b8fc9f30SRené van Dorst int speed;
1315656e7052SJohn Crispin struct device_node *of_node;
1316b8fc9f30SRené van Dorst struct phylink *phylink;
1317b8fc9f30SRené van Dorst struct phylink_config phylink_config;
1318656e7052SJohn Crispin struct mtk_eth *hw;
1319656e7052SJohn Crispin struct mtk_hw_stats *hw_stats;
1320ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
1321ee406810SNelson Chang int hwlro_ip_cnt;
132221089867SRussell King (Oracle) unsigned int syscfg0;
1323f63959c7SFelix Fietkau struct notifier_block device_notifier;
1324656e7052SJohn Crispin };
1325656e7052SJohn Crispin
1326656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */
1327656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[];
1328656e7052SJohn Crispin
mtk_is_netsys_v1(struct mtk_eth * eth)1329a008e2a8SLorenzo Bianconi static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
1330a008e2a8SLorenzo Bianconi {
1331a008e2a8SLorenzo Bianconi return eth->soc->version == 1;
1332a008e2a8SLorenzo Bianconi }
1333a008e2a8SLorenzo Bianconi
mtk_is_netsys_v2_or_greater(struct mtk_eth * eth)1334a008e2a8SLorenzo Bianconi static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)
1335a008e2a8SLorenzo Bianconi {
1336a008e2a8SLorenzo Bianconi return eth->soc->version > 1;
1337a008e2a8SLorenzo Bianconi }
1338a008e2a8SLorenzo Bianconi
mtk_is_netsys_v3_or_greater(struct mtk_eth * eth)13391953f134SLorenzo Bianconi static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth)
13401953f134SLorenzo Bianconi {
13411953f134SLorenzo Bianconi return eth->soc->version > 2;
13421953f134SLorenzo Bianconi }
13431953f134SLorenzo Bianconi
13449d8cb4c0SLorenzo Bianconi static inline struct mtk_foe_entry *
mtk_foe_get_entry(struct mtk_ppe * ppe,u16 hash)13459d8cb4c0SLorenzo Bianconi mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
13469d8cb4c0SLorenzo Bianconi {
13479d8cb4c0SLorenzo Bianconi const struct mtk_soc_data *soc = ppe->eth->soc;
13489d8cb4c0SLorenzo Bianconi
13499d8cb4c0SLorenzo Bianconi return ppe->foe_table + hash * soc->foe_entry_size;
13509d8cb4c0SLorenzo Bianconi }
13519d8cb4c0SLorenzo Bianconi
mtk_get_ib1_ts_mask(struct mtk_eth * eth)135203a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
135303a3180eSLorenzo Bianconi {
1354a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
135503a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
135603a3180eSLorenzo Bianconi
135703a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP;
135803a3180eSLorenzo Bianconi }
135903a3180eSLorenzo Bianconi
mtk_get_ib1_ppoe_mask(struct mtk_eth * eth)136003a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
136103a3180eSLorenzo Bianconi {
1362a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
136303a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE_V2;
136403a3180eSLorenzo Bianconi
136503a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE;
136603a3180eSLorenzo Bianconi }
136703a3180eSLorenzo Bianconi
mtk_get_ib1_vlan_tag_mask(struct mtk_eth * eth)136803a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
136903a3180eSLorenzo Bianconi {
1370a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
137103a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
137203a3180eSLorenzo Bianconi
137303a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG;
137403a3180eSLorenzo Bianconi }
137503a3180eSLorenzo Bianconi
mtk_get_ib1_vlan_layer_mask(struct mtk_eth * eth)137603a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
137703a3180eSLorenzo Bianconi {
1378a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
137903a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
138003a3180eSLorenzo Bianconi
138103a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER;
138203a3180eSLorenzo Bianconi }
138303a3180eSLorenzo Bianconi
mtk_prep_ib1_vlan_layer(struct mtk_eth * eth,u32 val)138403a3180eSLorenzo Bianconi static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
138503a3180eSLorenzo Bianconi {
1386a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
138703a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
138803a3180eSLorenzo Bianconi
138903a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
139003a3180eSLorenzo Bianconi }
139103a3180eSLorenzo Bianconi
mtk_get_ib1_vlan_layer(struct mtk_eth * eth,u32 val)139203a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
139303a3180eSLorenzo Bianconi {
1394a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
139503a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
139603a3180eSLorenzo Bianconi
139703a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
139803a3180eSLorenzo Bianconi }
139903a3180eSLorenzo Bianconi
mtk_get_ib1_pkt_type_mask(struct mtk_eth * eth)140003a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
140103a3180eSLorenzo Bianconi {
1402a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
140303a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE_V2;
140403a3180eSLorenzo Bianconi
140503a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE;
140603a3180eSLorenzo Bianconi }
140703a3180eSLorenzo Bianconi
mtk_get_ib1_pkt_type(struct mtk_eth * eth,u32 val)140803a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
140903a3180eSLorenzo Bianconi {
1410a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
141103a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
141203a3180eSLorenzo Bianconi
141303a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
141403a3180eSLorenzo Bianconi }
141503a3180eSLorenzo Bianconi
mtk_get_ib2_multicast_mask(struct mtk_eth * eth)141603a3180eSLorenzo Bianconi static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
141703a3180eSLorenzo Bianconi {
1418a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth))
141903a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST_V2;
142003a3180eSLorenzo Bianconi
142103a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST;
142203a3180eSLorenzo Bianconi }
142303a3180eSLorenzo Bianconi
1424656e7052SJohn Crispin /* read the hardware status register */
1425656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac);
1426656e7052SJohn Crispin
1427656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
1428656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
1429445eb644SLorenzo Bianconi u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
1430656e7052SJohn Crispin
14317e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
14327e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
14337e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
14349ffee4a8SSean Wang
1435502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth);
1436502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
1437502e84e2SFelix Fietkau void *type_data);
143805f3ab77SFelix Fietkau int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls,
143905f3ab77SFelix Fietkau int ppe_index);
144005f3ab77SFelix Fietkau void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
1441d776a57eSFelix Fietkau void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
1442502e84e2SFelix Fietkau
1443502e84e2SFelix Fietkau
1444656e7052SJohn Crispin #endif /* MTK_ETH_H */
1445