Home
last modified time | relevance | path

Searched +full:rk3288 +full:- +full:usb +full:- +full:phy (Results 1 – 25 of 46) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3066a-usb-phy
16 - rockchip,rk3188-usb-phy
17 - rockchip,rk3288-usb-phy
19 "#address-cells":
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
H A Drk3288-veyron-fievel.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-analog-audio.dtsi"
14 compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
15 "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
16 "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
17 "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
18 "google,veyron-fievel-rev0", "google,veyron-fievel",
19 "google,veyron", "rockchip,rk3288";
[all …]
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
18 arm-pmu {
[all …]
H A Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk3288-miqi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include "rk3288.dtsi"
12 compatible = "mqmaker,miqi", "rockchip,rk3288";
15 stdout-path = "serial2:115200n8";
23 ext_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <125000000>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk3288-r89.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/pwm/pwm.h>
9 #include "rk3288.dtsi"
13 compatible = "netxeon,r89", "rockchip,rk3288";
20 ext_gmac: external-gmac-clock {
21 compatible = "fixed-clock";
22 clock-frequency = <125000000>;
23 clock-output-names = "ext_gmac";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power-domain/rk3288.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/video/rk3288.h>
14 compatible = "rockchip,rk3288";
[all …]
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3128-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
42 arm-pmu {
[all …]
H A Drk3288-tinker.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /dts-v1/;
7 #include "rk3288-tinker.dtsi"
10 model = "Tinker-RK3288";
11 compatible = "rockchip,rk3288-tinker", "rockchip,rk3288";
14 stdout-path = &uart2;
19 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
24 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
26 rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
31 u-boot,dm-pre-reloc;
[all …]
H A Drk3288-phycore-rdk.dts2 * Device tree file for Phytec PCM-947 carrier board
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
47 #include <dt-bindings/input/input.h>
48 #include "rk3288-phycore-som.dtsi"
51 model = "Phytec RK3288 PCM-947";
52 compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
55 stdout-path = &uart2;
59 u-boot,dm-pre-reloc;
60 u-boot,boot0 = &emmc;
[all …]
H A Drk3288-rock2-square.dts2 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
42 #include "rk3288-rock2-som.dtsi"
46 compatible = "radxa,rock2-square", "rockchip,rk3288";
49 stdout-path = "serial2:115200n8";
52 ir: ir-receiver {
53 compatible = "gpio-ir-receiver";
55 pinctrl-names = "default";
56 pinctrl-0 = <&ir_int>;
60 compatible = "simple-audio-card";
[all …]
H A Drv1108.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/rv1108-cru.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
17 interrupt-parent = <&gic>;
27 #address-cells = <1>;
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
25 operating-points = <
[all …]
H A Drk3288-miqi.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 #include "rk3288.dtsi"
14 ext_gmac: external-gmac-clock {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <125000000>;
18 clock-output-names = "ext_gmac";
21 io_domains: io-domains {
22 compatible = "rockchip,rk3288-io-voltage-domain";
25 audio-supply = <&vcca_33>;
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3228-cru.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
[all …]
/openbmc/linux/arch/arm/mach-rockchip/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Tony Xie <tony.xie@rock-chips.com>
55 rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8); in rk3288_config_bootdata()
74 * if any usb phy is still on(GRF_SIDDQ==0), that means we need the in rk3288_slp_disable_osc()
75 * function of usb wakeup, so do not switch to 32khz, since the usb phy in rk3288_slp_disable_osc()
99 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR in rk3288_slp_mode_set()
100 * PCLK_WDT_GATE - disable WDT during suspend. in rk3288_slp_mode_set()
141 * In deep suspend we use PMU_PMU_USE_LF to let the rk3288 in rk3288_slp_mode_set()
237 "rockchip,rk3288-sgrf"); in rk3288_suspend_init()
244 "rockchip,rk3288-grf"); in rk3288_suspend_init()
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3288-board.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <dt-bindings/clock/rk3288-cru.h>
37 if (!fdt_node_check_compatible(gd->fdt_blob, 0, in rk3288_qos_init()
38 "rockchip,rk3288-tinker")) in rk3288_qos_init()
56 switch (cru->cru_glb_rst_st) { in rk3288_detect_reset_reason()
82 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); in rk3288_detect_reset_reason()
174 return -1; in board_init()
179 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { in board_init()
192 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()
198 #include <usb.h>
[all …]
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
61 bool "Support Rockchip RK3288"
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip usb PHY driver
5 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
10 #include <linux/clk-provider.h>
18 #include <linux/phy/phy.h>
40 /* bits present on rk3188 and rk3288 phys */
74 struct phy *phy; member
80 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, in rockchip_usb_phy_power() argument
85 return regmap_write(phy->base->reg_base, phy->reg_offset, val); in rockchip_usb_phy_power()
96 struct rockchip_usb_phy *phy = container_of(hw, in rockchip_usb_phy480m_disable() local
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
[all …]
/openbmc/u-boot/drivers/usb/phy/
H A Drockchip_usb2_phy.c1 // SPDX-License-Identifier: GPL-2.0+
25 * struct rockchip_usb2_phy_cfg: usb-phy port configuration
26 * @port_reset: usb otg per-port reset register
27 * @soft_con: software control usb otg register
28 * @suspend: phy suspend register
48 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
57 tmp = en ? reg->enable : reg->disable; in property_enable()
58 mask = GENMASK(reg->bitend, reg->bitstart); in property_enable()
59 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in property_enable()
61 writel(val, pdata->regs_phy + reg->offset); in property_enable()
[all …]

12