arm/dts/rk322x.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3228-cru.h>
11 #include <dt-bindings/thermal/thermal.h>
14 	#address-cells = <1>;
15 	#size-cells = <1>;
17 	interrupt-parent = <&gic>;
28 		#address-cells = <1>;
29 		#size-cells = <0>;
33 			compatible = "arm,cortex-a7";
36 			operating-points = <
40 			#cooling-cells = <2>; /* min followed by max */
41 			clock-latency = <40000>;
47 			compatible = "arm,cortex-a7";
54 			compatible = "arm,cortex-a7";
61 			compatible = "arm,cortex-a7";
68 		compatible = "simple-bus";
69 		#address-cells = <1>;
70 		#size-cells = <1>;
78 			#dma-cells = <1>;
80 			clock-names = "apb_pclk";
84 	arm-pmu {
85 		compatible = "arm,cortex-a7-pmu";
90 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
94 		compatible = "arm,armv7-timer";
95 		arm,cpu-registers-not-fw-configured;
100 		clock-frequency = <24000000>;
104 		compatible = "fixed-clock";
105 		clock-frequency = <24000000>;
106 		clock-output-names = "xin24m";
107 		#clock-cells = <0>;
111 		compatible = "mmio-sram";
113 		#address-cells = <1>;
114 		#size-cells = <1>;
116 		smp-sram@0 {
117 			compatible = "rockchip,rk322x-smp-sram";
120 		ddr_sram: ddr-sram@1000 {
121 			compatible = "rockchip,rk322x-ddr-sram";
127 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
130 		#address-cells = <1>;
131 		#size-cells = <0>;
132 		clock-names = "i2s_clk", "i2s_hclk";
135 		dma-names = "tx", "rx";
136 		pinctrl-names = "default";
137 		pinctrl-0 = <&i2s1_bus>;
142 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
145 		#address-cells = <1>;
146 		#size-cells = <0>;
147 		clock-names = "i2s_clk", "i2s_hclk";
150 		dma-names = "tx", "rx";
155 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
158 		#address-cells = <1>;
159 		#size-cells = <0>;
160 		clock-names = "i2s_clk", "i2s_hclk";
163 		dma-names = "tx", "rx";
168 		u-boot,dm-pre-reloc;
169 		compatible = "rockchip,rk3228-grf", "syscon";
174 		compatible = "snps,dw-apb-uart";
177 		clock-frequency = <24000000>;
179 		clock-names = "baudclk", "apb_pclk";
180 		pinctrl-names = "default";
181 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
182 		reg-shift = <2>;
183 		reg-io-width = <4>;
188 		compatible = "snps,dw-apb-uart";
191 		clock-frequency = <24000000>;
193 		clock-names = "baudclk", "apb_pclk";
194 		pinctrl-names = "default";
195 		pinctrl-0 = <&uart1_xfer>;
196 		reg-shift = <2>;
197 		reg-io-width = <4>;
202 		compatible = "snps,dw-apb-uart";
205 		clock-frequency = <24000000>;
207 		clock-names = "baudclk", "apb_pclk";
208 		pinctrl-names = "default";
209 		pinctrl-0 = <&uart21_xfer>;
210 		reg-shift = <2>;
211 		reg-io-width = <4>;
216 		compatible = "rockchip,rk3228-i2c";
219 		#address-cells = <1>;
220 		#size-cells = <0>;
221 		clock-names = "i2c";
223 		pinctrl-names = "default";
224 		pinctrl-0 = <&i2c0_xfer>;
229 		compatible = "rockchip,rk3228-i2c";
232 		#address-cells = <1>;
233 		#size-cells = <0>;
234 		clock-names = "i2c";
236 		pinctrl-names = "default";
237 		pinctrl-0 = <&i2c1_xfer>;
242 		compatible = "rockchip,rk3228-i2c";
245 		#address-cells = <1>;
246 		#size-cells = <0>;
247 		clock-names = "i2c";
249 		pinctrl-names = "default";
250 		pinctrl-0 = <&i2c2_xfer>;
255 		compatible = "rockchip,rk3228-i2c";
258 		#address-cells = <1>;
259 		#size-cells = <0>;
260 		clock-names = "i2c";
262 		pinctrl-names = "default";
263 		pinctrl-0 = <&i2c3_xfer>;
268 		compatible = "rockchip,rk3288-pwm";
270 		#pwm-cells = <3>;
272 		clock-names = "pwm";
273 		pinctrl-names = "default";
274 		pinctrl-0 = <&pwm0_pin>;
279 		compatible = "rockchip,rk3288-pwm";
281 		#pwm-cells = <3>;
283 		clock-names = "pwm";
284 		pinctrl-names = "default";
285 		pinctrl-0 = <&pwm1_pin>;
290 		compatible = "rockchip,rk3288-pwm";
292 		#pwm-cells = <3>;
294 		clock-names = "pwm";
295 		pinctrl-names = "default";
296 		pinctrl-0 = <&pwm2_pin>;
301 		compatible = "rockchip,rk3288-pwm";
303 		#pwm-cells = <2>;
305 		clock-names = "pwm";
306 		pinctrl-names = "default";
307 		pinctrl-0 = <&pwm3_pin>;
312 		compatible = "rockchip,rk3288-timer";
316 		clock-names = "timer", "pclk";
319 	cru: clock-controller@110e0000 {
320 		u-boot,dm-pre-reloc;
321 		compatible = "rockchip,rk3228-cru";
324 		#clock-cells = <1>;
325 		#reset-cells = <1>;
326 		assigned-clocks = <&cru PLL_GPLL>;
327 		assigned-clock-rates = <594000000>;
330 	thermal-zones {
331 		cpu_thermal: cpu-thermal {
332 			polling-delay-passive = <100>; /* milliseconds */
333 			polling-delay = <5000>; /* milliseconds */
335 			thermal-sensors = <&tsadc 0>;
355 			cooling-maps {
358 					cooling-device =
363 					cooling-device =
371 		compatible = "rockchip,rk3228-tsadc";
375 		clock-names = "tsadc", "apb_pclk";
377 		reset-names = "tsadc-apb";
378 		pinctrl-names = "init", "default", "sleep";
379 		pinctrl-0 = <&otp_gpio>;
380 		pinctrl-1 = <&otp_out>;
381 		pinctrl-2 = <&otp_gpio>;
382 		#thermal-sensor-cells = <0>;
383 		rockchip,hw-tshut-temp = <95000>;
388 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
390 		max-frequency = <150000000>;
394 		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
395 		fifo-depth = <0x100>;
396 		pinctrl-names = "default";
397 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
402 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
407 		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
408 		fifo-depth = <0x100>;
409 		pinctrl-names = "default";
410 		pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
415 		compatible = "rockchip,rk3288-dw-mshc";
417 		max-frequency = <150000000>;
421 		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
422 		bus-width = <8>;
423 		default-sample-phase = <158>;
424 		num-slots = <1>;
425 		fifo-depth = <0x100>;
426 		pinctrl-names = "default";
427 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
429 		reset-names = "reset";
433 	usb20_otg: usb@30040000 {
434 		compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
438 		hnp-srp-disable;
444 		compatible = "rockchip,rk3228-gmac";
447 		interrupt-names = "macirq";
452 		clock-names = "stmmaceth", "mac_clk_rx",
457 		reset-names = "stmmaceth";
462 	gic: interrupt-controller@32010000 {
463 		compatible = "arm,gic-400";
464 		interrupt-controller;
465 		#interrupt-cells = <3>;
466 		#address-cells = <0>;
476 		compatible = "rockchip,rk3228-pinctrl";
478 		#address-cells = <1>;
479 		#size-cells = <1>;
483 			compatible = "rockchip,gpio-bank";
488 			gpio-controller;
489 			#gpio-cells = <2>;
491 			interrupt-controller;
492 			#interrupt-cells = <2>;
496 			compatible = "rockchip,gpio-bank";
501 			gpio-controller;
502 			#gpio-cells = <2>;
504 			interrupt-controller;
505 			#interrupt-cells = <2>;
509 			compatible = "rockchip,gpio-bank";
514 			gpio-controller;
515 			#gpio-cells = <2>;
517 			interrupt-controller;
518 			#interrupt-cells = <2>;
522 			compatible = "rockchip,gpio-bank";
527 			gpio-controller;
528 			#gpio-cells = <2>;
530 			interrupt-controller;
531 			#interrupt-cells = <2>;
534 		pcfg_pull_up: pcfg-pull-up {
535 			bias-pull-up;
538 		pcfg_pull_down: pcfg-pull-down {
539 			bias-pull-down;
542 		pcfg_pull_none: pcfg-pull-none {
543 			bias-disable;
546 		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
547 			drive-strength = <12>;
551 			sdmmc_clk: sdmmc-clk {
555 			sdmmc_cmd: sdmmc-cmd {
559 			sdmmc_bus4: sdmmc-bus4 {
568 			sdio_clk: sdio-clk {
572 			sdio_cmd: sdio-cmd {
576 			sdio_bus4: sdio-bus4 {
585 			emmc_clk: emmc-clk {
589 			emmc_cmd: emmc-cmd {
593 			emmc_bus8: emmc-bus8 {
606 			rgmii_pins: rgmii-pins {
624 			rmii_pins: rmii-pins {
637 			phy_pins: phy-pins {
644 			i2c0_xfer: i2c0-xfer {
651 			i2c1_xfer: i2c1-xfer {
658 			i2c2_xfer: i2c2-xfer {
665 			i2c3_xfer: i2c3-xfer {
672 			i2s1_bus: i2s1-bus {
686 			pwm0_pin: pwm0-pin {
692 			pwm1_pin: pwm1-pin {
698 			pwm2_pin: pwm2-pin {
704 			pwm3_pin: pwm3-pin {
710 			otp_gpio: otp-gpio {
714 			otp_out: otp-out {
720 			uart0_xfer: uart0-xfer {
725 			uart0_cts: uart0-cts {
729 			uart0_rts: uart0-rts {
735 			uart1_xfer: uart1-xfer {
740 			uart1_cts: uart1-cts {
744 			uart1_rts: uart1-rts {
750 			uart2_xfer: uart2-xfer {
755 			uart2_cts: uart2-cts {
759 			uart2_rts: uart2-rts {
764 		uart2-1 {
765 			uart21_xfer: uart21-xfer {
773 		u-boot,dm-pre-reloc;
774 		compatible = "rockchip,rk3228-dmc", "syscon";
784 		u-boot,dm-pre-reloc;
785 		compatible = "rockchip,rk3228-msch", "syscon";