usb/phy/rockchip_usb2_phy.c

1 // SPDX-License-Identifier: GPL-2.0+
25  * struct rockchip_usb2_phy_cfg: usb-phy port configuration
26  * @port_reset: usb otg per-port reset register
27  * @soft_con: software control usb otg register
28  * @suspend: phy suspend register
48 	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
57 	tmp = en ? reg->enable : reg->disable;  in property_enable()
58 	mask = GENMASK(reg->bitend, reg->bitstart);  in property_enable()
59 	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);  in property_enable()
61 	writel(val, pdata->regs_phy + reg->offset);  in property_enable()
67 	struct dwc2_plat_otg_data *pdata = dev->pdata;  in otg_phy_init()
74 		if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node,  in otg_phy_init()
75 					      of_id->compatible) == 0) {  in otg_phy_init()
76 			phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;  in otg_phy_init()
86 	pdata->priv = phy_cfg;  in otg_phy_init()
88 	property_enable(pdata, &phy_cfg->soft_con, false);  in otg_phy_init()
91 	property_enable(pdata, &phy_cfg->port_reset, true);  in otg_phy_init()
93 	property_enable(pdata, &phy_cfg->port_reset, false);  in otg_phy_init()
99 	struct dwc2_plat_otg_data *pdata = dev->pdata;  in otg_phy_off()
100 	struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;  in otg_phy_off()
103 	property_enable(pdata, &phy_cfg->soft_con, true);  in otg_phy_off()
105 	property_enable(pdata, &phy_cfg->suspend, true);  in otg_phy_off()